Linux/DRA74: Media clock implementation

Hi
Can you describe your use case requirements - what is the end application, intended functionality with AVB

Hi Sriram,

Please consider first the simple example of a single live audio stream from an EAVB talker to a single EAVB listener using AVTP Audio Format (AAF – formerly Simple Audio Format or SAF).  Analog to Digital (A/D) signal conversion at the talker provides digital sound samples, at 48kHz, to an application; the application provides these samples to the EAVB stack on the talker; they are packetized and transmitted over the EAVB network to a listener where the EAVB stack delivers the sound samples to an application; the application delivers them for Digital to Analog (D/A) conversion, at 48kHz, and the sound is played on a speaker.  Since the 48 kHz clocks on the talker and on the listener are provided by two separate and independent oscillators, it is extremely unlikely that they will run at precisely the same speed – as a result, it would be expected that either underrun or overrun of digital samples would eventually occur at the listener.  Further, if there are multiple listeners, it would be expected that they would drift relative to each other over time.

Please let me know  if you have questions.

Thanks,

Mythili Ram

The DRA7x SoC enables compliance with the IEEE 1588-2008 standard for a precision clock synchronization protocol. For media clock synchronization I assume you will be using IEEE1588 or some variants such as 802.1AS PTP protocol.

The DRA7x TRM has details on how to enable and use the time synch feature

Under Section:

24.10 Gigabit Ethernet Switch section

Time synch info is present under:

24.10.4.10 Common Platform Time Sync (CPTS)

24.10.4.10.2 CPTS Initialization provides details on CPTS module initialization

24.10.4.10.5.5 Ethernet Port Events : Provides details on events generated when spl time sync packets are sent or received.

For selecting the clock source for the CPTS reference clock refer Table 3-1024. CM_GMAC_GMAC_CLKCTRL

The field CLKSEL_RFT enable CPTS reference clock source selection.

Would recommend you select L3_ICLK initially as its clock config would be handled as part of regular system initialization. Once you have functionality enabled you can select a different clock source depending on your usecase needs.

Hi Badri,

We have already achieved gPTP syncronization between all nodes.Now I m trying to do media clock syncronization.

Which DPLL (DPLL_ABE, DPLL_VIDEO, DPLL_HDMI)should be used for Media clock synchronization?

Please guide us the changes required in CPTS module to achieve media clock recovery.

Thanks,

Mythili Ram

CPTS module provides hardware support for 802.1ASRev and other family of IEEE1588 protocols which allows synchronization of common Wall Clock across the network. By media clock recovery I assume you are using IEEE1722 (AVBTP) or something analogous. My understanding is the IEEE1722 by design does not expect the media clock to be synchronized with the Wall Clock time that is provided by 802.1AS. This allows multiple independent media streams to be present. So I did not understand the question about selecting DPLL for CPTS.
Note that for clock adjustment to account for drift you will need external Voltage Controlled Crystal Oscillator (VCXO) that is controlled by SPI or some other interface. The SoC itself does have any inbuilt module for clock drift adjustment.
Can you please explain what issue you are facing after implementing 802.1ASrev and IEEE1722 in your system and that may help to resolve the issue.

Hello,
Sorry to bother you. Do you have additional info on the issue you are facing wrt to implementing 802.1ASrev and IEEE1722 in your system

Hi,

We are using ALSA framework for capturing and playing the audio(1722 Audio use case). CRF AVTPDUs with a type field of CRF_AUDIO_SAMPLE convey the sampling time of an audio sample clock(as mentioned in IEEE 1722 2016).
We tried to get the media clock as an device entry like ptp clock so that we can adjust the frequency as we did for gPTP clock frequency adjustment , but we failed.

Thanks,
Mythili R