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Can the C6A816x use commodity (64-Bit) SO-DIMMs or DIMMs?

To keep costs down and simplify layout it would be great if standard 64-bit DDR2/DDR3 SO-DIMMs or DIMMs were usable with the C6A816x/AM389x.

The DDR interfaces are 32-bit wide.  Is there a way to link them or have them both clock their data at the same time.

I have not been able to deduce from the latest datasheet (19 Oct 2010) or Technical Reference Manual (29 Oct 2010) whether all the memory on a standard 64-bit DDR2/DDR3 SO-DIMM would be usable.

  • Hello,

    These devices do not support a direct connection to 64-bit DDR DIMMs.

    Regards,
    Marc Pyne

  • I would like to connect as much fast memory as possible to the C6A816x and as cheaply as possible.
     
    My design will need to be viable at low to medium volumes so a memory module would be the best option.  With regard to TI's choice of 32bit DIMM for the C6A816x EVM,JEDEC has only one 32bit SODIMM standard and it is slow and not stocked anywhere:
     
    http://www.jedec.org/standards-documents/technology-focus-areas/memory-module-design-file-registrations
     
    http://www.jedec.org/content/ep2-2100-32bit-sodimm-0
     
     
    Any ideas you can throw out there would be appreciated.  My options appear to be 1) use half of a DDR3 SODIMM module and pay with increased power consumption, or 2) use four discrete DDR2 ICs and pay with reduced memory throughput.
     
     
    Does the design of the C6A816x guarantee that both memory interfaces are never simultaneously active?  That might allow some sort of control signal OR'ing.  Or am I missing something?

  • As Marc Pyne indicated, DIMMs are not supported, of any kind.

    Memory for these systems is planar, meaning soldered onto the same PCB as the DSP.  There are two independent 32 bit DDR EMIFs than can be run as DDR2 or DDR3.  For DDR2, two x16 devices are supported per EMIF.  This results in a smaller PCB foot print.  For DDR3, in addition to higher speed, two x16 devices or 4 x8 devices can be used.

    The DIMMs used on the DDR2 EVM are special in that they contain two independent 32 bit DDR2 memory systems.  They are not standard, nor cost effective for production systems.  The only thing these DIMMs share with standard DIMMs is the edge fingers and DIMM socket (they are not pin compatible either).  The DDR3 EVM will have planar memory.

    There is no memory throughput issue here.  The two EMIFs cannot be tied together because they operate independently.  Each interface is 32 bits wide, for a combined memory bus width of 64 bits.

    -Mike

  • Thank you for your reply.  I would appreciate it if you could humor just one more idea.

    JEDEC has a planar DDR3 SODIMM standard (Raw Card F) which is available at retail (Kingston KHX1600C9S3K2 at Amazon).  I am assuming this SODIMM is planar as only Raw Card F supports PC3-12800+ and has 16 ICs.  The 2GB module has 14 address lines and the module has 2 ranks.  Assuming power consumption is not an issue then one fourth of such a SODIMM (4 ICs from one rank) can be connected to a single 32-bit C6A816x memory interface if the following are true:

    1) The C6A816x DDR3 PHY is designed for a fly-by topology connection to four x8 DDR3 DRAM ICs

    2) The DDR3 PHY interface can drive the inputs of all 16 DDR3 ICs on a planar DDR3 SODIMM

    3) The DDR3 PHY can function properly if the C6A816x's DDR3 power supply rail is not being used (the SODIMM will require a 1.5A+ external power supply)

     

    Depending on requirements, the connection of a 2GB SODIMM to each 32-bit memory interface in order to have 512MB of DDR3 SDRAM might be a viable option.  At the very least this might be useful during prototyping.

    So, is it possible or are there other considerations I am overlooking?

  • I don't know of any other way to say it: No.

    This topic was discussed internally during product development and the conclusion was the waste and extra address drive required for supporting 64 bit DIMMs was not justified.  In addition, a single 64 bit interface was passed over in favor of two 32 bit interfaces due to higher bandwidth efficiency when the memory is shared amongst the various SOC internal data paths

    -Mike

  • Thank you for your reply and for discussing the design decision.  It is good to know the TMS320C6A816x was designed with low power consumption in mind.

  • Hi

    Can I just reopen this discussion.

    From the EVM circuits it is clear that DIMMs are used, but yet all of the comments from TI employees state that DIMMs cannot be used.

    And the errata for the device states that DDR3 doesn't work anyway! I guess this will be resolved in the next silicon spin.

    Can anyone clarify?

    Thanks.

  • Graham,

    The EVM does use a DDR2 DIMM but it is not a standard commodity DIMM, it is a custom board build for the EVM.

    You can also assume that DDR3 is solved in a new silicon spin.

    Iain

  • Adding to Iain's comments, the custom DIMM was done as an expedited temporary measure to allow SW development while the DDR3 issues were analyzed and fixed.  

    These early boards have not been characterized and the only expectation for them is operation at room temp with the particular device installed in them.  They are tested before shipment to ensure they work.  Providing a design spec that is expected to work over PVT for any device installed into any board meeting our layout spec is a whole other matter and a lot more difficult.  For this, we are providing a planar solution for both DDR2 and DDR3.  The planar solution offer better, more controlled loads for the DDR controller than is possible with the DIMM.

    -Mike

  • Thanks.

    I assume the C6A8168 works with DDR3. Are chip samples relatively easy to get hold of?

    Do you have an idea on the availabilty of an 8168 based EVM (with a DDR3 planar solution)?

  • Graeme,

    Please contact your local TI Sales rep for sample and EVM availability.

    Regards,
    Marc

  • Hi Marc, Michael and Iain,

    Just trying to sum up, since reading through the tread not being naively English speaking the conclusion might unfortunately still not be 100% clear I think.

    I hope I'm correct saying that neither DDR2 nor DDR3 DIMMs will be supported on any revision on the chips.Neither now, nor in the future. The chips are solely designed to work with planar memory (both DDR2 and DDR3) mounted on the the same PCB as the C6A816x itself - Correct? At least this is my current understanding :-)

    Can one of you please confirm that this understanding is correct once and for all putting this into stone and closing this thread - As well for people reading it sometime in the future...

    Best regards and thanks in advance
      Søren

    PS: I'm hope my understanding is correct - Otherwise this post might actually end out harming more than it helps :-)

  • This is the simplest way to put it.  A standard JEDEC DDR2 or DDR3 DIMM is 64 bits wide with a common address bus.  The 816x has two independent 32 bit DDR controllers.  Thus, while there are 64 data bits, there are also two independent address buses, thus they are incompatible with an industry standard JEDEC DIMM.  There is no cost benefit to a non-standard DIMM and there is additional loading and trace length from the DIMM connector, therefore it makes no sense to use DIMMs of any kind with 816x for PCBs.

    -Mike

     

  • Hi Michael,

    Thanks for your reply. I'm glad that you could confirm that my understanding was correct and I as well agree that their would be no benefit from using DIMM memory modules unless you would had wanted a configurable system where you (at a later time) being a system builder could equip it with the amount of memory needed for the given application - This unfortunately is not an option...

    I think that people mainly got the idea of using DIMM modules from the fact that there is a DIMM socket on the EVM (not standard layout I know), which kind of confused people. Especially put together with the non working DDR3 memory for the first revision...

    Anyway thank for your confirmation - I'm happy that my understanding was correct and I hope that this post will now end this thread once and for all :-)

    Best regards and thanks again
      Søren