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c6454 in Master I2C boot

MA3000
Prodigy 50 points
Other Parts Discussed in Thread: XIO2001

Hi,

Based on the c6454 datasheet:

"Once all the power supplies are within valid operating conditions, the POR pin must remain asserted (low) for a minimum of 256 CLKIN2 cycles. The PLL1 controller input clock, CLKIN1, and the PCI input clock, PCLK, must also be valid during this time. PCLK is only needed if the PCI module is being used."

In my case the PCI clock is provided by the XIO2001 bridge which holds the PCI clock as long as the PCI-e reset line is asserted (100msec'), long after the POR is de-asserted. Based on the requirement above, I need to hold the POR asserted after the PCI-e reset is de-asserted, however this will cause miss - enumeration of the DSP by the BIOS. Pls. explain.

Thanks,

           Meir

 

  • 0
    TI__Intellectual 2620 points

    Unfortunately the C6454 PCI module needs a running clock to properly initialize after reset. For this use case, an external clock source needs to be fed to XIO2001 PCI bus clock input (CLK pin). Anyone of XIO2001 seven PCI bus clock output (CLKOUTn) can be used to drive the C6454 PCI clock (PCLK).