• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 98 subscribers
  • Views 550 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

XEVMK2LX: Maximum supported ADC data rate

XEVMK2LX: Maximum supported ADC data rate

Majid Boloorian
Prodigy 220 points
Part Number: XEVMK2LX
Other Parts Discussed in Thread: RFSDK, DAC38J84, ADC14X250

Hi Joe

Thanks for the fast response. I notice that using the DFE will limit the throughput. In our application we do not necessarily need the DFE functionality. We would like to get raw data into the DSP (in a ping-pong buffer in memory) as fast as possible. We need a time synchronized dual ADC configuration (similar to IQ receiver).

What is the maximum dual ADC sample rate (12-14bit resolution) that can be used with the 66AK2L06 EVM. From the information provided it appears that we should be able to use all 4 Rx JESD lanes on the first FMC connector and get 737.28Msps per ADC channel in dual channel configuration. Is this correct? Is there a subsequent speed limitation at the IQN2 that will prevent this?

We also need a DAC in our system to be driven from the 66AK2L06 EVM. The DAC identified is DAC37J82. Can the DAC EVM be driven from the other FMC connector or do we need the deterministic latency card to get the DAC and ADC better synchronized?

Thank you

  • 0
    TI__Mastermind 37500 points
    Hello,
    There are several places where the Serdes, DFE Rx, DFE Baseband, IQN2 Baseband interface have limitations.
    There is no wideband bypass of Receive chain or Transmit Chain.

    The Receive JESD lanes can support 4 lanes at 7.3728Gbps, however the Rx data has to go into the JESD block and into DFE. DFE has one Rx port with an input that runs at DFE clock rate, 245.76e6/n, or 368.64e6/n.

    Since this is 32bits wide, you can have (1) ADC with 2 real samples transferred at 368.64e6, with a sample rate of 737.28e6 (not in RFSDK)
    737.28e6 real -> converted to 368.64 complex, and must be decimated by 2 in Rx 184.32e6, and decimated by 3/2 in DDUC for 122.88e6 BB output.

    You can review the TI designs and the DFE User Guide " www.ti.com/.../spruhx8a.pdf " for further information

    You can have (1) 368.64e6 complex input.
    The Rx block decimates by 2 to 184.32e6.
    The DDUC decimates by 3/2 for 122.88e6 BBoutput.
    One stream can be converted to 2 channels with decimate by 2 in DDUC, for 92.16e6 BB output.

    You can have (2) 184.32e6 complex inputs, typically in this case, the Rx or DFE block decimates by 2.
    The 2 channels would have a 92.16e6 BB output rate.

    The Tx and Rx side typically have the same BB channel rate
    1 channel -> 1 stream -> 1 channel 122.88e6
    2 channel -> 1 channel / stream (2 total streams) -> 2 channel 92.16e6

    TIDEP-0060 uses the RFSDK, 1 antenna, 1 channel, DAC38J84, ADC14x250
    TIDEP-0081 uses the RFSDK, 2 streams, 2 channels, DAC38J84, ADC32RF8x

    Note: the programming of the dataconverters is done before the RFSDK startup sequence.
    If you desire to use other dataconverters, you need to make the same JESD format, or contact the third party providers
    for custom work, Azcom Ltd, CommAgility Ltd.

    Regards,
    Joe Quintal
  • 0 in reply to Radio-Joe
    Prodigy 220 points
    Thanks for the additional information. The Rx data throughput constraints are clear now.