In the C6742 datasheet sprs587a, there is a specification for EMA_CLK maximum frequency (minimum period, actually) for the synchronous SDRAM mode.
But there is no similar specification for the EMA_CLK maximum frequency (minimum period) for the asynchronous mode.There are notes that mention an example of E=10ns if EMA_CLK=100MHz, but that does not tell me if that is the limit or even if that is valid.
Other similar parts (C6748) do specify this value, and it is not the same max clock frequency for sync and async modes, so I did not want to make that assumption here.
Thanks for your help,
RandyP