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AM4376: RTOS bootloader entry point

Part Number: AM4376

According to this wiki: 

#1. About the Entry point of Bootloader: 

        * For bootloader Entry point is usually 0x402f0000

  • For the app the entry point is usually 0x80000000.

According to TRM, on GP device, on-chip RAM start from 0x4030_0000, why the entry point is 0x402f_0000? I tried on my AM437x IDK board REV1.3A, address of 0x402F_0000 can't be accessed.  Is it always available for ROM bootloader not for user?

#2. TRM page 223, about QSPI boot: 

5.2.6.7 QSPI
QSPI EEPROMs or QSPI flashes have an EEPROM or NOR flash backend and they connect to the
device using the serial QSPI protocol.
The device will operate in memory mapped mode.
ROM Code will execute ISW directly from QSPI Flash because it is configured in memory mapped mode

 is QSPI xIP device? is there more detail how it is configured in memory map mode? and how it works?

#3. 0x3000_0000: QSPI CS0 Maddrspace 1 space, what is mean of Maddrspace?

  • The RTOS team have been notified. They will respond here.
  • Tony,

    Tony Tang said:
    According to TRM, on GP device, on-chip RAM start from 0x4030_0000, why the entry point is 0x402f_0000? I tried on my AM437x IDK board REV1.3A, address of 0x402F_0000 can't be accessed.  Is it always available for ROM bootloader not for user?

    Yes, that is correct. This explained in the ROM L3 RAM Usage map that is shown in the TRM as shown below. this reqion in the ROM is reserved for secure and core startup services. If you see the startup code that runs on the core that sets up interrupt vector table and cache, mmu is placed there. The main SBL function is usually not locate in that region.

    is QSPI xIP device? is there more detail how it is configured in memory map mode? and how it works?

    QSPI and GPMC NOR are treated as direct memory mapped boot modes. This is possible to implement as the interface unlike NAND or SPI NOR supports direct memory access to the memory using the memory regions as shown below:

    The QSPI XIP direct addressing is a feature that is supported by the QSPI interface and the flash memory. The serial Flash memory mapping is seen as another memory in the product memory map. this is referred to in the TRM as memory mapped mode in QSPI chapter. This is also supported by our Processor SDK QSPI drivers using "QSPI_OPER_MODE_MMAP" mode so you check this operation there and how this mode differs from the command/configuration mode.

    Tony Tang said:
    #3. 0x3000_0000: QSPI CS0 Maddrspace 1 space, what is mean of Maddrspace?

    It corresponds to the chip select memory address space, but AM437x only has a single chip select (CS0) so it refer to it QSPI CS0 Maddrspace which you can use when QSPI flash is configured to be in Quad mode.

  • From the TRM:

    5.2.3.2.1 Downloaded Image (ISW)
    This area is used by the Public ROM Code to store the downloaded Initial SW. The downloaded image
    can be up to 271KB on GP Device. It resides from 0x402F4000 (0x402F0400 for PG1.1) to 0x40337C00
    in GP device.

    Note: If ROM boots using USB_MS boot mode, then the image can reside only from 0x40300000. This
    limits the maximum image size while using USB_MS boot mode to 220KB.

  • Sorry, just noticed you were asking about QSPI specifically. The 0x402F4000 address is common for boot modes like MMC where the image gets copied by the ROM into internal RAM. Looks like Rahul answered at nearly the same time as me, but with a better answer! :-)
  • Thanks Rahul,

    Quick question:

    #1. use Maddrspace address can directly access QSPI space, which is faster between Maddrspace address access and command/configuration mode? seems ROM use Maddrspace, boot(second bootloader) use command/configuration mode.

    #2. Can user change QSPI_CLK in boot during boot running on QSPI?

    #3. Can QSPI Maddrspace support DMA directly access like access general memory in address auto increase mode?

  • Thanks Griffis,
    you are always helping.