Tool/software: TI-RTOS
Hi,
I have an issue with HW timer 13 having an unexpectedly large timing variation of 960 us. This could be reproduced with Timer14 and Timer15 as well.
My setup is with AM5728 running Linux on A15 and SYS/BIOS on DSP1, DSP2, IPU1 and IPU2.
Processor SDK: processor_sdk_rtos_am57xx_4_00_00_04
PDK: pdk_am57xx_1_0_7
I have explicitly disabled timer13 in the dts on the Linux side:
timer13: timer@48828000 {
compatible = "ti,omap5430-timer";
reg = <0x48828000 0x80>;
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer13";
status = "disabled";
};
I have reduced the test so DSPs and IPUs just have an idle task and DSP1 sets up the timer and monitors its operation. The code to setup and monitor the timer is attached. This code is invoked within a task.
The code sets up timer 13 to generate a 20Hz signal with 50% duty cycle. It maps the timer 13 interrupt from the crossbar to the DSP IRQ 53. It measures and prints the interval between interrupt calls every 20 interrupts. The actual implementation uses a GPIO and reproduces the same issue when viewed on a scope.
The timer configuration is the following:
HW_WR_REG32(l4perBaseVirt + CM_L4PER3_TIMER13_CLKCTRL, 0x2);
while ((HW_RD_REG32(l4perBaseVirt + CM_L4PER3_TIMER13_CLKCTRL) & (0x00030000)) != 0x0) ;
timer13Base = SOC_TIMER13_BASE;
TIMERModeConfigure(timer13Base, TIMER_AUTORLD_NOCMP_ENABLE);
TIMERPreScalerClkDisable(timer13Base);
TIMERCounterSet(timer13Base, MY_TIMER_RELOAD_VALUE);
TIMERReloadSet(timer13Base, MY_TIMER_RELOAD_VALUE);
TIMERPostedModeConfig(timer13Base, TIMER_NONPOSTED);
TIMERReadModeConfig(timer13Base, TIMER_READ_MODE_NONPOSTED);
TIMERIntStatusClear(timer13Base, TIMER_INT_TCAR_IT_FLAG | TIMER_INT_OVF_IT_FLAG | TIMER_INT_MAT_IT_FLAG);
TIMERIntEnable(timer13Base, TIMER_INT_OVF_EN_FLAG);
TIMEREnable(timer13Base);
Here's a sample output of the test application which measures the interval between timer interrupts and prints the min (L), max (U) and 6 first collected values:
[ 552.251] Collected L:24953 U:25920 24959 25920 24960 24959 24960 24960
[ 552.277] Collected L:24953 U:25920 24959 25920 24960 24959 24960 24960
[ 552.303] Collected L:24953 U:25920 24959 25920 24960 24959 24960 24960
[ 552.329] Collected L:24953 U:25920 24959 25920 24960 24959 24960 24960
From these traces, it appears the interval between interrupts is usually 24960 or 25920, which gives a 960us spacing. These values are also multiples of 960 so I'm guessing there's something delaying the interrupts but I couldn't find out what it is.
I could also reproduce the issue on IPU1 with the same 960us spacing.
How can I make the timer interrupt fire my_timer.zipat a reliable time?
