Does anyone have a suggestion for how to measure the amount of DSP CPU I am using with my firmware? A rough percentage, as displayed by the typical operating system, would be helpful.
I am using CSL, but not DSP/BIOS or anything that high level. My application is based around several channels of I/O, all running at 125 kHz with a 128-sample-frame window. Thus, my code needs to repeat every 976.5625 Hz. What I want to determine is whether I am using more cycles than are available. The period is 1.024 ms, and the C5506 is running at the maximum 108 MHz, meaning that I have 110,592 clock cycles available. I am calling FFT routines, several DSP assembly-optimized subroutines, and a couple of USB API endpoints. I have counted cycles on many of the individual routines, but I have no idea what the total cycles for everything might be. There's also the consideration that 4 channels of DMA and USB are eating cycles outside the actual execution, at least if there is contention for bus resources then DMA would add cycles, which is certainly true while the FFT is running.
Any suggestions?