• State Resolved
  • Locked Locked
  • Replies 2 replies
  • Subscribers 98 subscribers
  • Views 412 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

How to get 48KHz/16bit sample rate on McASP from 24MHz clock?

MikeH
Guru 15580 points
Other Parts Discussed in Thread: OMAP-L138

I am using the Logic PD Experimenter with OMAP-L138 SOM, which has a 24.00MHz  clock source. It appears that a buffered version of this 24.0MHz clock (AUXCLK)  is used to drive the McASP. It also appears that this AUXCLK is divided by HCLKRDIV and CLKRDIV to achieve the desired RCLK rate. I am using the McASP to generate an I2S interface to an AIC3106. My application calls for 16-bit stereo channels of 48000 samples per second (16x2x48000=1.536MHz RCLK). How do I generate a 1.536MHz RCLK from the 24.0MHz AUXCLK since this requires a divisor of 15.625? What values should I use for HCLKRDIV and CLKRDIV?

Thx,

MikeH

  • 0
    TI__Mastermind 28891 points

    Your analysis is correct for the case in which you use "internal" clocking, meaning, you use AUXCLK.  However, notice that there is also a 24.576MHz clock source on the board that feeds into AHCLKX.  You can set AHCLKX as input and use the internal dividers to get the frequency you are looking for (24.576/1.536 = 16).  I have not looked at the LogicPD BSL test files recently, but I believe this is what they do (<bsl install dir>bsl/tests/experimenter/audio).

  • 0 in reply to Gus Martinez
    Guru 15580 points

    Gus,

    Ahhh...you are correct. What had me confused was they label the pin (J1-pin 89) "uP_UART1_CTSn" on the SOM board instead of "M_AHCLKX" , which is what feeds it from the baseboard.

    Thanks for the feedback.

    MikeH