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66AK2H14: Reset Behaviour

Bruno B
Expert 1290 points

Part Number: 66AK2H14

Hi,

Some questions and comments :

1) Reading the 66AK2H14 datasheet SPRS866G, the Keystone II ARM boot loader user guide SPRUHJ3, the  Keystone II architecture ARM core PAC user guide SPRUHJ4, and Hardware design guide SPRABV0 , makes finaly things mixing-up a little bit. Therefore i come up with basic questions :

- Do you confirm that RESETFULL signal resets both ARM cores and DSP cores ? meaning that ARM cores and DSP cores will re-start  executing RomBootLoader in the same manner as upon power-up., while all internal registers are reset, except for DEVSTAT

- Do you confirm that RESET signal does the same as RESETFULL except for isolated modules (actually only SRIO and Smartreflex) and PLL, meaning that ARM cores and DSP cores will re-start  RomBootLoader in the same manner as upon power-up, based upon DEVSTAT,SRIO,smartreflex and PLL current settings.? I also note that DDR3 content is generally lost (probably because DDR controler is reset to default values)

- Finally do you confirm that LRESET DOES NOT impact  ARM cores at all, but DO re-start DSP cores execution from their RomBootLoader. Therefore In case where the device boot mode was set to ARM MASTER, do you agree that activating LRESET will finaly result in a situation where DSP cores are waiting in idle state at the end of RBL while ARM cores are continuing as if nothing had happened ?

2) In datasheet 10.2.3.8 there is the description of RESET_STAT register and the reference to a (GR) "global reset". Since this new wording is not explained anywhere else in the document , could you confirm that we are speaking here of POR or RESETFULL events ONLY ?

3) In datasheet §11.4.2 we can read

which finaly reveals to be true ONLY if the PLL controler RSISO initialization has been programmed accordingly. If not, PLL is reset to default and must be reprogrammed (see §5.1.3 of the hardware design guide)

4) in the ARM core PAC user guide, there is the table 3-1 mentioning "Global chip 0" and "Global chip 1".

What are Chip 0 and Chip 1 representing ? Which resources are initiating "Global chip 0 warm reset" and "Global chip 1 warm reset" ?

With best regards, and many thanks for your help,

Bruno

  • 0
    TI__Guru**** 161600 points
    I'm looking into this. I will post my feedback by EoB tomorrow.

    Best Regards,
    Yordan
  • 0
    TI__Guru**** 161600 points
    Hi Bruno,

    Resets are explained in: Table 11-9. Reset Type:
    RESETFULL -> Resets the entire chip including the test and emulation logic. The device configuration pins are latched only during power-on reset.
    So to answer your questions:
    Do you confirm that RESETFULL signal resets both ARM cores and DSP cores ?


    Yes, your understanding is correct.

    RESET -> Hard reset resets everything except for test, emulation logic, and reset isolation modules. This reset is different from power-on reset in that the PLL Controller assumes power and clocks are stable when a hard reset is asserted. The device configurations pins are not relatched. Emulation-initiated reset is always a hard reset. By default, these initiators are configured as hard reset, but can be configured (except emulation) as a soft reset in the RSCFG Register of the PLL Controller. Contents of the DDR3 SDRAM memory can be retained during a hard reset if the SDRAM is placed in self-refresh
    mode.

    Do you confirm that RESET signal does the same as RESETFULL except for isolated modules (actually only SRIO and Smartreflex) and PLL, meaning that ARM cores and DSP cores will re-start RomBootLoader in the same manner as upon power-up, based upon DEVSTAT,SRIO,smartreflex and PLL current settings.?


    Again your understanding is correct. The cores will reset.

    LRESET -> Resets the C66x CorePac, without disturbing clock alignment or memory contents. The device configuration pins are not relatched

    Finally do you confirm that LRESET DOES NOT impact ARM cores at all, but DO re-start DSP cores execution from their RomBootLoader. Therefore In case where the device boot mode was set to ARM MASTER, do you agree that activating LRESET will finaly result in a situation where DSP cores are waiting in idle state at the end of RBL while ARM cores are continuing as if nothing had happened ?


    Yes.

    2) In datasheet 10.2.3.8 there is the description of RESET_STAT register and the reference to a (GR) "global reset". Since this new wording is not explained anywhere else in the document , could you confirm that we are speaking here of POR or RESETFULL events ONLY ?


    Global reset is an event that resets the entire device, not just part of it (like LRESET). So POR or RESETFULL are global reset events. Also the SOFTRESET can be a global reset event.

    which finaly reveals to be true ONLY if the PLL controler RSISO initialization has been programmed accordingly. If not, PLL is reset to default and must be reprogrammed (see §5.1.3 of the hardware design guide)


    In case of misalignment between user guide and the datasheet, the recommendation is to always refer to the Datasheet, as it is the most frequently updated document.

    4). This is internal for the ARM Core Pack only. Note that this is a general document and most likely refers to the ARM0 and ARM1 cores.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Expert 1290 points

    Hi Yordan,

    Thank you for the time you took to explain, and confirm my understanding.

    By the way, did you receive the reply I did the 20th of August to my previous POST about LRESET/LRESETNMIEN.... ?

    I had no answer from you to this topic.

    Best regards,

    Bruno