Part Number: 66AK2L06
Hi,
I would like to know about the PCIe inbound transfer configuration in 66AK2L06 using PCIe0 . We have DSP as RC and FPGA as EP. Configuration is for 32bit pcie mode. The source code we are referring to is pcie_sample.c (pdk pcie example project). I have done the following modification in the code and tried to read from 0x50100000.But no data is received in gdstBuf_dstBuf.buf. Inbound address translation is enabled.
I would like to know about the PCIe inbound transfer configuration in 66AK2L06 using PCIe0 . We have DSP as RC and FPGA as EP. Configuration is for 32bit pcie mode. The source code we are referring to is pcie_sample.c (pdk pcie example project). I have done the following modification in the code and tried to read from 0x50100000.But no data is received in gdstBuf_dstBuf.buf. Inbound address translation is enabled.
barCfg.location = pcie_LOCATION_LOCAL;
barCfg.mode = pcie_RC_MODE;
barCfg.base = 0x50100000;
barCfg.prefetch = pcie_BAR_NON_PREF;
barCfg.type = pcie_BAR_TYPE32;
barCfg.memSpace = pcie_BAR_MEM_MEM;
barCfg.idx = 1;
ibCfg.ibBar = 1;
ibCfg.ibStartAddrLo = 0x50100000;
ibCfg.ibOffsetAddr =( uint32_t)pcieConvert_CoreLocal2GlobalAddr ((uint32_t)gdstBuf_dstBuf.buf);
ibCfg.region = 0;
ibCfg.ibStartAddrLo = 0x50100000;
ibCfg.ibOffsetAddr =( uint32_t)pcieConvert_CoreLocal2GlobalAddr ((uint32_t)gdstBuf_dstBuf.buf);
ibCfg.region = 0;
cmdStatus.ibXltEn = 1;
gdstBuf_dstBuf is allocated in L2SRAM
Anyone please let me know whether anything else is to be done in configuration for receiving data in local buffer from FPGA.
Thanks
Sreejaya