AM3352: DDR clock problem

Hi Egbert,

The DDR clock speed is configured in u-boot/board/ti/am335x/board.c file, check functions:

get_dpll_ddr_params()
sdram_init()

How do you define that you are running at 303MHz?
"But the amount of EE has not changed, the same is 300 CLK。" - what does this mean?

Regards,
Pavel

Hi Pavel ,

and thank you for your reply.

"But the amount of EE has not changed, the same is 300 CLK。" - what does this mean?

I mean Hardward member help me verify frequence singel is not 400 CLK by oscilloscope .

BR
Egbert Liu

Egbert,

You need to dump DDR PLL registers to check if this update (303MHz to 400MHz) is applied:

CM_CLKSEL_DPLL_DDR

CM_CLKMODE_DPLL_DDR

CM_DIV_M2_DPLL_DDR

Check these registers before update and after update and compare the results. For more info you can refer to AM335x TRM, sections 8.1.6.11 DDR PLL Description, 7.3.3.2 Clock Control

Note also that just changing first parameter (from 303 to 400) of config_ddr() function is not enough. You need also adjust your DDR chips settings for that speed. See how AM335x ICE board TMDSICE3359 is setup for 400MHz DDR_CLK:

void sdram_init(void)

{

else if (board_is_icev2())

config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data, &ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data, 0);

}

static const struct ddr_data ddr3_icev2_data = {
    .datardsratio0 = MT41J128MJT125_RD_DQS_400MHz,
    .datawdsratio0 = MT41J128MJT125_WR_DQS_400MHz,
    .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE_400MHz,
    .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA_400MHz,
};

static const struct cmd_control ddr3_icev2_cmd_ctrl_data = {
    .cmd0csratio = MT41J128MJT125_RATIO_400MHz,
    .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,

    .cmd1csratio = MT41J128MJT125_RATIO_400MHz,
    .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,

    .cmd2csratio = MT41J128MJT125_RATIO_400MHz,
    .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT_400MHz,
};

static struct emif_regs ddr3_icev2_emif_reg_data = {
    .sdram_config = MT41J128MJT125_EMIF_SDCFG_400MHz,
    .ref_ctrl = MT41J128MJT125_EMIF_SDREF_400MHz,
    .sdram_tim1 = MT41J128MJT125_EMIF_TIM1_400MHz,
    .sdram_tim2 = MT41J128MJT125_EMIF_TIM2_400MHz,
    .sdram_tim3 = MT41J128MJT125_EMIF_TIM3_400MHz,
    .zq_config = MT41J128MJT125_ZQ_CFG_400MHz,
    .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY_400MHz |
                PHY_EN_DYN_PWRDN,
};

Refer to the below pointers for more info:

Regards,
Pavel

Hi Pavl,

I modify board.c file the below 2 routine content : get_dpll_ddr_params() , sdram_init()

The original file 303CLK can be boot normally without modification, but it cannot be turned on after modifying 400 CLK these two places.

Where do I need to modify the values of these third files?  

CM_CLKSEL_DPLL_DDR

CM_CLKMODE_DPLL_DDR

CM_DIV_M2_DPLL_DDR

If I want to dump CM_WKUP status offset: 0x44E0_0400 0x44E0_04FF , How to do by UART putty ?

=========================get_dpll_ddr_params()==============================

const struct dpll_params *get_dpll_ddr_params(void)
{
int ind = get_sys_clk_index();

if (board_is_evm_sk())
return &dpll_ddr3_400MHz[ind]; /*Rank20180824 Tune CLK 400*/
else if (board_is_bone_lt() || board_is_icev2())
return &dpll_ddr3_400MHz[ind];
else if (board_is_evm_15_or_later())
return &dpll_ddr3_303MHz[ind];
else
return &dpll_ddr2_266MHz[ind];
}

=====================sdram_init()================================


void sdram_init(void)
{
if (board_is_evm_sk()) {
/*
* EVM SK 1.2A and later use gpio0_7 to enable DDR3.
* This is safe enough to do on older revs.
*/
gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(GPIO_DDR_VTT_EN, 1);
}

if (board_is_icev2()) {
gpio_request(ICE_GPIO_DDR_VTT_EN, "ddr_vtt_en");
gpio_direction_output(ICE_GPIO_DDR_VTT_EN, 1);
}

if (board_is_evm_sk())
config_ddr(400, &ioregs_evmsk, &ddr3_data, /*Rank20180824 Tune CLK 400*/
&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
else if (board_is_bone_lt())
config_ddr(400, &ioregs_bonelt,
&ddr3_beagleblack_data,
&ddr3_beagleblack_cmd_ctrl_data,
&ddr3_beagleblack_emif_reg_data, 0);
else if (board_is_evm_15_or_later())
config_ddr(303, &ioregs_evm15, &ddr3_evm_data,
&ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
else if (board_is_icev2())
config_ddr(400, &ioregs_evmsk, &ddr3_icev2_data,
&ddr3_icev2_cmd_ctrl_data, &ddr3_icev2_emif_reg_data,
0);
else if (board_is_gp_evm())
config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_evm_emif_reg_data, 0);
else
config_ddr(266, &ioregs, &ddr2_data,
&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
}
#endif

Besides changing the clock frequency, you must also change the DDR timings as explained here:
processors.wiki.ti.com/.../AM335x_EMIF_Configuration_tips
processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3

This is a step-by-step tutorial:
processors.wiki.ti.com/.../Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack

Egbert Liu said:

The original file 303CLK can be boot normally without modification, but it cannot be turned on after modifying 400 CLK these two places.

Where do I need to modify the values of these third files?  

CM_CLKSEL_DPLL_DDR

CM_CLKMODE_DPLL_DDR

CM_DIV_M2_DPLL_DDR

These are not files, these are 3 registers, which are modified by u-boot, in setup_dplls(void) function.

static void setup_dplls(void)
{
    const struct dpll_params *params;

....

params = get_dpll_ddr_params();
    do_setup_dpll(&dpll_ddr_regs, params);
}

You do not need to modify these 3 registers manually, you just need to check these to verify your u-boot is correct.

Egbert Liu said:

If I want to dump CM_WKUP status offset: 0x44E0_0400 0x44E0_04FF , How to do by UART putty ?

One of the options is to enter into u-boot prompt and use md command, this is what I have on AM335x TI EVM:

U-Boot SPL 2017.01-gc68ed086bd (Mar 26 2018 - 15:08:11)
Trying to boot from MMC1
reading uboot.env

** Unable to read "uboot.env" from mmc0:1 **
Using default environment

reading u-boot.img
reading u-boot.img
reading u-boot.img
reading u-boot.img


U-Boot 2017.01-gc68ed086bd (Mar 26 2018 - 15:08:11 -0400)

CPU  : AM335X-GP rev 2.1
Model: TI AM335x EVM
DRAM:  1 GiB
NAND:  256 MiB
MMC:   OMAP SD/MMC: 0, OMAP SD/MMC: 1
reading uboot.env

** Unable to read "uboot.env" from mmc0:1 **
Using default environment

<ethaddr> not set. Validating first E-fuse MAC
Net:   cpsw, usb_ether
Hit any key to stop autoboot:  0
=> md 0x44e00434 1
44e00434: 00000001                               ....
=> md 0x44E00440 1
44e00440: 00006503                               .e..
=> md 0x44e00494 1
44e00494: 00000007                               ....
=> md 0x44e004a0 1
44e004a0: 00000222                               "...

Thus I have the values: M=101, N = 3, M2 = 2. As I have 24MHz main crystal freq (CLKINP), I have 303MHz for DDR3.

DDR3_CLK = (M/(N+1)) * CLKINP * (1/M2)

const struct dpll_params dpll_ddr3_303MHz[NUM_CRYSTAL_FREQ] = {
        {505, 15, 2, -1, -1, -1, -1}, /*19.2*/
        {101, 3, 2, -1, -1, -1, -1}, /* 24 MHz */
        {303, 24, 1, -1, -1, -1, -1}, /* 25 MHz */
        {303, 12, 2, -1, -1, -1, -1}  /* 26 MHz */
};

Other options are to put printf() in the u-boot code, thus printing these registers values or attach JTAG emulator and dump the registers in CCStudio.

 

Regards,
Pavel

 

Hi Pavel,

I have a question and suddenly want to ask

We used pure Am335x SDK set as motherboard Starter kit DDR3 Timing 302 CLK for used my customer board can boot on the system. if I want to 400 CLK

Why can SDK pure kernel code, not to auto setting and auto config 400 CLK select DDR3 parameter frequency function?

Because I have checked the TRM Spec mentioned in the file that it can support 400CLK.　

So the TI vendor did not write this feature　，Is there any limitations on the AM335X itself ? 　

＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝＝

another question，

I tried to modify the DDR3L through the CCS program using the file you provided earlier.

My understanding is that adjusting the gel file parameters requires CCS to import the <DDR3_slave_ratio_search_auto.out> file to complete.

But I still can't find an operation procedure on how to import this file into the CCS debug environment?
So I encountered difficulties and could not smoothly adjust the 400 CLK of DDR3.

Have you described more detail about the steps to load related files to the CCS tool?


BR
Egbert Liu

Hi Pavel,

and thank you for your reply.

I want to try to adjust below each value of the yellow field of this table to 400clk module, and reference to the <Table 7-225. SDRAM_TIM_1 Register field Descriptions> of TRM specification.

but I don`t have found any about DDR3 400 CLK setting description, only have register meaning explanation.

could I ask which information can refer to set this of data the table?

BR

Egbert

Hi Biser,

thank you for your reply.

I searched the DDR3 memory datasheet, but I did not find the parameters of the data that the following 2 Excel files can match.

1. AM335x_DDR_register_calc_tool.xls

2. RatioSeed_AM335x_boards.xls

I would appreciate it if you could take a moment to explain how to find key value match the excel file something to me

below file is DDR datasheet 

2Gb_1_35V_DDR3L_MT41K128M16JT-125.pdf

BR

Egbert Liu

Egbert,

Per mine understanding, RatioSeed_AM335x_boards.xls should be filled with values based on your custom board DDR3 design. You should not search these values in DDR3 chip datasheet, but get these from your HW designer.

Regarding AM335x_DDR_register_calc_tool.xls, for example, DDR3L-1600 -125, tRP is 13.75ns

Regards,
Pavel

If you have no more questions related to the subject, please close/verify/resolve this thread.

Regards,
Pavel