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RTOS/AM5746: SMP mode

Kaka
Guru 24520 points
Part Number: AM5746
Other Parts Discussed in Thread: SYSBIOS,

Tool/software: TI-RTOS

Hi TI Experts,

Please let me confirm the following question.

[Question]
Would you please explain the behavior of SMP/SYSBIOS when it will follow procedure?
1. Call the Hw_disable on Core 0 (Correspond to Inter-Core Lock）
2. Call the Core_HwiEnable on Core1 (Request the "Inter-Core-Lock" on Core 1)

If you have any questions, please let me know.

Best regards.
Kaka

  • 0
    TI__Guru**** 393215 points
    The RTOS team have been notified. They will respond here.
  • 0 in reply to lding
    Guru 24520 points
    Hi Eric,

    I have already checked those documents and post, but I could not find the answer for my question.
    Could you please help us?

    Best regards.
    Kaka
  • 0
    Guru 24520 points

    Part Number: AM5746

    Tool/software: TI-RTOS

    Hi TI Experts,
    I have posted the similar question but I had a mistake for my question. So, please let me confirm this similar question again.

    [Question.1]
    Would you please teach me the way or API to do the inter-lock request in case of using the SMP mode on SYSBIOS?

    [Question.2]
    If the inter-lock can be done by calling the API, what kind of processing is actually done for each cores when calling this API? (Or how is SYSBIOS implemented this behavior?)

    For example:(This may be not correct)
    1. Call the Hw_disable(or Core_HwiEnable()) on Core 0
    　(This meaning is "Request to do the Inter-Core Lock”）
    2. Core1 will set the CPSR.I(bit7) by detecting this request
    　（My customer would like to know the actually behavior like this)

    If you have any questions, please let me know.
    Best regards.
    Kaka

  • 0 in reply to Kaka
    TI__Guru** 116560 points
    Kaka,

    We have looped on the SYSBIOS team to provide guidance here but it is unclear on what is the intended implementation. Are you trying to set barrier between cores, synchronization between cores or is the intent to run a particular HWI in the system on a specific core or just to understand how the inter-core mechanism works in SMP mode?

    Core_lock and unlock in SMP mode is implemented using GateSMP in SYSBIOS. You can check the implementation of this in the source file:
    bios_6_xx_xx_xx\packages\ti\sysbios\family\arm\a15\smp\Core.c

    the GateSMP uses preload a gate word in ARM shared cache and then uses assembly instruction DMB to setup a memory barrier. Please refer to detailed implementation here:
    bios_6_52_00_12\packages\ti\sysbios\family\arm\v7a\smp

    Since the cache is shared in SMP mode, the other core doesn`t have to do anything as far as I can tell but the BIOS team can confirm my understanding.

    There is additional details on setting up memory and task barriers in SMP mode that have been discussed between Ashish and Marcus on this thread
    e2e.ti.com/.../1557090

    Hope this helps.

    Regards,
    Rahul
  • 0 in reply to Rahul Prabhu
    Guru 24520 points

    Hi Rahul,

    Thank you for your support. I think customer would like to know just to understand how the inter-core mechanism works when calling the Hwi_disable and Core_HwiEnable in SMP mode. So, could you teach me what action/process will be taken when simply calling the Hwi_disabled or Core_HwiEnable in SMP mode?

    Best regards.
    Kaka

  • 0 in reply to Kaka
    TI__Mastermind 18260 points

    Kaka,

    I'm not sure if you're wanting SMP implementation information for the A15s or the Ducati M4s on the AM5746 device.

    As Rahul said, Hwi_disable() for SMP uses Core_lock(), which itself uses GateSmp_enter().

    GateSmp_enter() has different implementations for A15 & Ducati.  A15 uses:

    ti/sysbios/family/arm/v7a/smp/GateSmp.c

    Ducati uses:

    ti/sysbios/family/arm/ducati/GateSmp.c

    So you can take a look for yourself in these files to see the implementation.

    Core_hwiEnable(), for Ducati, is in:

    ti/sysbios/family/arm/ducati/Core__epilogue.h

    It has different implementations depending on TI compiler vs GCC.

    For A15, see:

    ti/sysbios/family/arm/a15/smp/Core__epilogue.h

  • 0 in reply to Robert Tivy
    TI__Guru* 96960 points
    Can I mark this as resolved?
  • 0 in reply to ToddMullanix
    Guru 24520 points
    Hi Todd,

    Yes. I marked it.

    Best regards.
    Kaka