RTOS/DRA71: VIP MODULE

user5183370

Intellectual 510 points

Part Number: DRA71

Tool/software: TI-RTOS

Now we have a projcet using the VIP module to connect the BT656 video.

The path is as bellow:

Analog Camera -> AD device -> J6 VIP port (BT656).

The probleam is that the Bt656 timing form the AD device is not standard, which the filed bit(bit6) in the SAV & EAV is not correct.

BIT7(fixed)

BIT6（F）

BIT5(V)

BIT4(H)

BIT3

BIT2

BIT1

BIT0

And the frame captured from the VIP module is error.

Please help confirm that does not the video capture based on the VIP module will check this bit ?

over 7 years ago

0 Sivaraj R3681 over 7 years ago

TI__Expert 4935 points

The input signal to the VIP should follow the BT656 standard. Any other timing is not supported by VIP. Can you check if you can use discrete sync for capture? Check if the ADV signal can output HSYNC and VSYNC signal and that can be connected to VIP.

0 user5183370 over 7 years ago in reply to Sivaraj R3681

Intellectual 510 points

Hi
1. Please check this blog:
e2e.ti.com/.../656942 user:335970

I asked a related qustion about the non standard BT656 timing,the ansower is that the VIP module can support the non standard BT656 timing.

Please help check .

2. As we need to connect Multiple videos in one port , we need to use BT656 timing .what the consequence if the filed bit in SAV & EAV is error ?

0 Brijesh Jadav over 7 years ago in reply to user5183370

TI__Guru**** 476595 points

Hi,

Non-standard here means you could have difference frames size, which are not matching matching with the NTSC/PAL resolution. But the SAV/EAV codes must be exactly same as supported in BT656. These are the codes, that VIP uses to identify framing signals.

Rgds,

Brijesh

0 user5183370 over 7 years ago in reply to Brijesh Jadav

Intellectual 510 points

Hi.

Could you help explain the "codes" . How the error field affect the frame ? Or do you have some materials about it ?

In our condition ,the value of field bit is still 0/1, but the sequence of 0 /1 is error. , it maybe 0,0,0,1,1,0,1...ad so on.

According to my understanding ,this doesn't affect the identification of the frame .

0 Brijesh Jadav over 7 years ago in reply to user5183370

TI__Guru**** 476595 points

Hi,

It is explained in '9.4.5.7.2 Sync Words' in the TRM.
Essentially bit6 denotes field id bit, this should be toggling for interlaced input and should be 0 for progressive input. In your case, since it is not constant, VIP thinks that it is interlaced input and treats input stream as fields.. This could be the reason why capture frame is not correct.
What do you see in the captured frame? How different it is from original frame?

Regards,
Brijesh

0 user5183370 over 7 years ago in reply to Brijesh Jadav

Intellectual 510 points

"In your case, since it is not constant, VIP thinks that it is interlaced input and treats input stream as fields."

The VIP module may treat th stream as field ,but the frame size is still 1280*720*2(In our application ,the frame resoulition IS 1280*720 ,UYVY.) .

What is captured should be the whole frmae with random filed bit. The frame struct should not be changed? right?

The error frams is as bleow:

0 user5183370 over 7 years ago in reply to user5183370

Intellectual 510 points

Hi
Additionally, the SAV should be at the red line in the picture.
The relal frame is start at the read line ,but the frame we capture is splitted into three parts.

0 Brijesh Jadav over 7 years ago in reply to user5183370

TI__Guru**** 476595 points

Are you sure it is just F bit, which is changing? It seems even H bit is changing. Otherwise there will not be any horizontal changes..

Rgds,
Brijesh

0 user5183370 over 7 years ago in reply to Brijesh Jadav

Intellectual 510 points

Hi

As we communicated with AD decive , in there scheme it just the F bit is error, H bit is correct .

0 Brijesh Jadav over 7 years ago in reply to user5183370

TI__Guru**** 476595 points

Could you please check if VIP reported any bit errors? There are some error status register..
Lets first check if VIP reported any error.

Rgds,
Brijesh

0 user5183370 over 7 years ago in reply to Brijesh Jadav

Intellectual 510 points

I will test it again and catch some status regs.

And we want to ask some questions which the AD device want to check :

Does J6 processor check option bits of BT.656 as below? ( also, Is it possible to swap EAV and SAV flag? )

Bit3-0(P3P2P1P0)
0000
1101
1011
0110
0111
1010
1100
0001

0 Brijesh Jadav over 7 years ago in reply to user5183370

TI__Guru**** 476595 points

No, No way to swap SAV and EAV flags..

Rgds,
Brijesh

Processors

Processors forum

RTOS/DRA71: VIP MODULE