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Clock configuration on DM6435

MattLipsey
Genius 3575 points

I am configuring the (myriad) clocks on the DM6435 and had a few questions. (reference SPRU978, figure 4-1 on page 31)

1) There is no vpbe on the DM6435, so can I disable the BPDIV on PLL1 & the PLLDIV2 on PLL2?  Does this save any power?

2) It seems that the BPDIV on PLL2 is used for the DDR2 VTP block, but I couldn't locate any frequency limitations.  What should my output frequency range be for this block?

3) Is the vpfe maximum pclk input frequency sysclk2/2 (sysclk / 3 /2), or is there a hard limit in addition? 

Thanks for any insight.

  • Genius 3575 points

    As I am digging into the clock configuration, I think I found a datasheet/code mismatch.  The DM643x datasheets give a required minimum stabilization wait value of 150 usecs (table 6-17, page 161 on the June 2008 updated tmsdm6435 datasheet) as opposed to the other two wait periods which specify numbers of clock cycle waits.  Yet in the gel file and in the board support library pll initialization functions from the dvsdk, between enabling the pll and setting the go bit there is only a call to _wait(150), which waits clock cycles, not microseconds.  Is this a bug or a datasheet typo?  Also, I noticed both the gel file and the bsl init functions wait an additional 2000 clocks after leaving pll bypass mode.  Is this (or any wait) necessary, or just a cut/paste leftover?

    Again, thanks for any insight.