Part Number: TDA2P-ACD
Hi Team,
could you please help answer customer question?
I have some questions regarding the timing information that needs to be programmed into REG0 and REG1 of the CSI2 PHY registers.
We are connecting a TDA2PX with a DS90UB954 that is generating a test pattern on all four lanes.
During CSI2 PHY initialization I can see that the STOP_STATE (Register CAL_CSI2_TIMING_0) and that the RESET_DONE (CAL_CSI2_COMPLEXIO_CFG_0) are reached, when using a CSI2 data rate of 400 Mbps (which means a CSI2 clock frequency of 200MHz). When using a CSI2 data rate of 800 Mbps (CSI2 clock frequency of 400MHz), then this is not the case.
I am wondering if I have understood the calculations of the timing parameters in CSI2 PHY registers 0 and 1 correctly (TRMv1.0, pp. 3440-3442).
For THS_TERM:
From the TRM: “Programmed value = floor(20 ns/DDR_CLK), where DDR_CLK is the period of the CSI-2 I/O lane rate. Default value: 4 (for 400 MHz).”
This default value is correct(per calculation), if 400MHz is meant for the data rate and the actual clock on the line is 200MHz (=5ns period). Is the assumption correct, that the period of the actual CSI2 clock lane has to be used here (and not the data rate)?
For THS_SETTLE:
From the TRM: “Programmed value = floor(105 ns/DDR_CLK) + 4, where DDR_CLK is the period of the CSI-2 I/O lane rate. Default value: 39 (for 400 MHz).”
For the default value of 39, DDR_CLK would need to be 333.3 MHz. This is not the case as per description. Assumption: For a CSI2 clock of 200MHz (400 Mbps data rate) the value would be 25. For a CSI2 clock of 400MHz it would be 46. Is this assumption correct?
For TCLK_SETTLE:
From the TRM: “Programmed value = max[3, ceil(155 ns/CTRLCLK period) –1] Default value: 14 (for 96 MHz)”
The calculation is straight forward, though in the PDK the value is calculated by the following formula: “temp = (((Float32)260U / (Float32)DPHY_FUNCTIONAL_CLK_PERIOD) - (Float32)2U);”
This would mean a value of 22 instead of 14. Which one is correct?
The calculation for TCLK_TERM is also different from what it is in the TRM, but in this case, both calculations lead to the same result.
For TCLK_DIV:
From the TRM: “Divide factor for CTRLCLK for CLKMISS detector Programmed value = ceil (15ns/CTRLCLK Period) – 1 Default value: 1 (for 96 MHz)
CLKMISS detection time = (5*TCLK_DIV+1)*(CTRLCLK period) < 60ns
Note: Only the CTRLCLK frequencies that satisfy above relationship are allowed. Typically, 96MHz will be used at CTRLCLK.”
Though with the default value of 1, the CLKMISS detection time is 62.5ns, which is greater than 60ns. Is this okay?
Main questions:
- For THS_TERM/THS_SETTLE: Should the period of the data rate or the CSI2 clock (half of data rate) be used for the calculations?
- Which value for TCLK_SETTLE is correct (14 or 22)?
We would appreciate your help to clarify the above calculations!
Note: File used from PDK (01_10_00_08) to compare the calculations: vpshal_calCsi2Tda2px.c
Thanks,
Needhu
