L1 data is configured for normal, write-through, cacheable; L2 is disabled.
Simple test steps:
- Enable data cache
- Clean and invalidate data cache
- Read from a predefined location to fill a cache line
- Disable data cache
- Write to the previously cached location
- Enable data cache
- Read from the same location. The expectation was that writing should not change cache contents. But it does.
Tried using PMU counters. The 0x04 event counter (table 3-97 on p. 3-85 of the ARM DDI 0344k) indicates data cache accesses with data cache disabled.
Thanks,
Ilya
