• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 485 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TMS320C6655: how to handle the DDRCLK pin when DDR3 is not used

UNA
Mastermind 7980 points

Hi,

There was a comment that it is necessary to supply DDRCLK even if DDR is not used for C6655 in the following thread.


However, the hardware design guide(SPRABI2C) states that DDRCLKp is connected to CVDD and DDRCLKn is connected to GND.

which one is correct?

Best Regards,
H.U

  • 0
    TI__Mastermind 42545 points

    Hi H.U,

    That was the original guidance we published but it was found that, while the part will operate correctly without the DDR clock present, the part will draw additional current in that state. It was discovered that the DDR clock is needed to ensure that the DDR portion of the device has been reset into a known good state. We will be updating the documentation as soon as we can spare the resources. 

    Regards, Bill