DM355 booting issues

Sudarshan,

Here are some suggestion to help w/your debug:

1) have you probed the reset signal w/a scope to see if indeed the device is out of reset?

2) is your terminal window being used baudrate matching the UART Boot mode? it should be 115200.

3) can you please probe the the BTSEL pins to ensure that the switch setting is indeed setting these pins to the proper voltage level?

4) Are you able to connect using JTAG and  Code Composer Studio (CCS)?(if available)

5)  Can you please confirm it is DM355 and not DM365?

6) Which silicon revision of the device is this?

thanks,

miguel

Miguel,

Here is the answer to your feedback:

1. Yes, reset signal fine, used reset switch to reset it many times to see any toggling happening on the TXD0.

2. yes, Baudrate is 115200. But i am unable to see any signal toggling (BOOTME) on the TXD0 from DSP.

3. Yes, these signal are fine as per the Datasheet and is in UART mode.

4. No, I have no JTAG with me here.

5. I am using DM355(I rechecked it while I am writing the mail)

6. Silicon revision is 1.1(TMS320DM355ZCE270 is the part no).

Please advice.

Regards

Sudarshan

Sudarshan,

thanks.

Have you ensured that the you are flashing the UBL/uBoot correctly to your device? How did you flashed the UBL/Uboot to your board?

Here are some external wikis on flashing utilities used for TI's evm.

http://processors.wiki.ti.com/index.php/Serial_Boot_and_Flash_Loading_Utility

regards,

miguel

Miguel,

Thanks for your support.

yes,  am able to flash UBL and access the mDDR through JTAG, but unable to boot it from the flash.

Boot config pins are(flash has UBL) :

1. BITSEL0,BITSEL1 = 0,0 for NAND (1,1 for UART)

2. AECFG0 = 1

AECFG1 = 0

AECFG2 = 1

AECFG3 = 1

unable to see any activity on flash while booting from NAND flash. when set for UART booting,I dont see any activity on the UART0 : TXD pin.

Please advice.

Regards

Sudarshan

Sudarshan,

Can you try the following:

1) power up your board

2) connect JTAG CCS (please remove any Gel files to prevent this from running during your connect)

3) Read the following register from the device via JTAG in a memory window: 0x01c40014(bootcfg register)

bits[7:6] will confirm the btsel pins settings read by the device

bits[3:0] will tell you the AECFG[3:0] being read by the device.

This is so we can confirm that everything is properly latched during boot, since your external pulls on the pins might not be appropriate.

Also, one very important thing to note however is the following careabout note that we have on the GPIO0 PIN.

"Note: The GIO000 pin must be held high during NAND boot for the boot process to fuction properly."

regards,

miguel

Miguel,

Thanks for the mail.

here is my abservation:

1. Powered the board.

2. Connected JTAG with CCS (gel file removed)

3. BOOTCFG Register value:0000010D  for NAND Boot and 000001CD for UART Boot.

Latching of the signals for NAND boot and UART Boot is ok and GIO0 bit is 1 for these modes. That means the boot config is ok.

4. Flashing the board is fine(with UBL,U-Boot)

5. Accessing the mDDR is fine.

I was in Texas Instruments,Bangalore for debugging the board.

With these are fine, unable to see BOOTME on the UART or from Flash boot.

I would like to share the schematics and get it reviewed from you,since the design is confidential, if you share your email ID, I would send it across.

My skype ID : sudar_ns

Please advice.

-Sudarshan

Miguel,

In addition to above points: While flashing the device(Flash), I can see the signals toggling(read/Chipselect). While Booting from Flash, i dont see any signal toggling. I reviewed the schematics again, I dont see any mistake.

Is there any issues with clocking or PLL ?

Regards

Sudarshan