Hi,
I have a situation where a single 8KByte block of DARAM has to be accessed from eight DMAs so as you understand, timing, latency and dma element ordering does play a large role here.
It is stated in spruft2.pdf that dma transfer elements (DMA element tasks) are served in a round robin fashion regarding the channels (2.11).
Yet it does not clearly distinguish if it means all 16 channels are in the same round robin or that rule is for the four channels within each DMA controller.
Also it does not specify entirely what rule apply between them when two or more DMA controllers are competing for the same 8K block, is it a similar round robin yet in this case not for channels but at controller level?
So my questions are these
1. please clear if my understanding is right that within a controller only one channel is active at any given clock cycle, the active channel has to finish its current dma element in order for the controller to proceed to the next channel and so on in the round robin, 1,2,3,4,1,2,3,4 etc.
2. Is there a possibility that all four controllers can concurrently, in the same clock cycle, compete (via one of their channels) for the same 8K DARAM or SARAM block? if that can be done then what is the rule of servicing all of them?
Christos
