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TMS320C6416T: EDMA transfer

Part Number: TMS320C6416T

Hi,

The customer transfer with EDMA. FPGA generates interrupt to DSP every 0.5ms. DSP responds in time and starts the EDMA transfer. TCC is set to10. CIPRL=0x400,CIERL=0x7FF after the transfer completed. But the DSP cann't enter the interrupt handle function. The phenomenon happens once in 1 hours after power on.

Please help to analyze!

  • Hi,

    Which Processor SDK RTOS version are you using?

    Best Regards,
    Yordan
  • Hi,

    He used the CSL in ccs3.3. Are there any suggestions that can help him to analyze?

  • Nancy,

    The most important information here is from the opposite of "The phenomenon happens once in 1 hours after power on". The opposite is that the system is behaving correctly most of the time. Since the interrupt occurs very often, the basic construction of the system is valid and is working well.

    I will assume that the failure is permanent once it occurs. In other words, once the interrupt handler function is not entered, it will never occur again. I also assume that you have two interrupt functions: FPGA interrupt handler and EDMA interrupt handler. The system may have other interrupt handlers, and the interaction (which ones may overlap, etc.) of all of them must be understood.

    The customer must consider the system operation to try to understand what is causing this failure. They must determine what events occur at about the same time as the failure (use logic analyzer to view activity), what system changes fix or make the failure worse (change the DSP speed faster or slower, add dummy loads inside interrupt handlers to slow things down). They can add GPIO pulses inside the interrupt handlers to allow visibility to the logic analyzer but keep in mind that these can slow down the handler a lot (do not use read/modify/write for GPIO toggle, only use a 'mirror' variable or fixed value write).

    The system analysis must also consider how the EDMA is being used for other transfers. If other transfers occur at about the same time, they can interact or interfere with the FPGA EDMA channel's operation by delaying it or causing interrupts to occur too close in terms of time between them. This can lead to problems clearing the interrupts in the CIPRL register, for example.

    Often, a problem like this will come from the DMA transfer ending too late so another transfer is already to begin. There may be some error condition registers you can check. Please refer to the EDMA User Guide for any possible error indications that might help.

    Depending on the complexity of the product and system design and application code, it may be impractical to give more specific debug guidance through the forum. Your customer will need to do the debug to figure out what is happening. But any further detail you can send may help Yordan's team to give you more help.

    Regards,
    RandyP
  • Here are some register status.The CIPRL register's bit10 is set,but has no corresponding IFR (bit8) set.

    And the EDMA_INT is set to INT8,FPGA interrupt is set to INT4.