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DDR2 Initialization Sequence

Andy Jump53114
Prodigy 130 points


We have been looking at the code base for the EVM and comparing it with the latest datasheet and the Setting up AM35x SDRC Registers wiki and have found some discrepancies. Could someone outline the correct procedure for initialising DDR2 or confirm my procedure below - the wiki does not give the full procedure as a step by step guide, just a generic what has to be set.

I belive that the following procedure should work:

1. Set up all the registers and leave reg_initref_dis bit set to 1.

2. Reset the DDR PHY, wait for the REG_RESET_PHY to clear and run the VTP and wait for VTP_READY to be set

3. Set reg_initref_dis to 0.

I'm guessing that if you set up some of the registers after running the DDR PHY setup and VTP that it won't matter. I'm also assuming from the way the TRM is worded that reg_initref_dis is the bit that actually kicks off the DDR2 initialisation sequence. If this is the case then it follows that all the registers setting that affect the LMRs during initialisation have to be set up prior to reg_initref_dis being cleared.

Can someone please comment on my interpretation of the sequence.

  • 0
    TI__Guru* 87850 points

    Andy, actually the x-loader is probably your best source to get the right sequence.  In general, the sequence should be

    1.  Setup DDR PHY control registers

    2. Reset the PHY (using IODFT_TLGC) and wait till complete

    3. Perform a VTP calibrate

    4. Configure EMIF

    a.  Setup timing registers (SDRAM_TIM_xxx)

    b.  Setup Power control reg (PWR_MGMT_CTRL)

    c. Setup refresh rate (SDRAM_REF_CTRL)

    d. Setup SDRAM configuration register (SDRAM_CONFIG)

     

    When you write to SDRAM_CONFIG, this kicks off the hardware sequence which initializes the DDR interface (the details are described in the TRM). 

    Step 3 is not in the linux code because this was a recent enhancement to our DDR initialization sequence (and is another reason why it isn't in the TRM yet).  The VTP calibration sequence performs a calibration on the DDR I/Os.  A lot of designs may work without this calibration (as in the case of the EVM), but you will likely see more robust performance with the calibration.

    Let me know if this addresses everything.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 180 points

    Hello James,

     

    we are experiencing at the moment the same problem as Andy - initializing SDRAM from Bootloader.

    I did the the sequence from above, and it still does not work.

    In a TRM it is mentioned, that the Shadow registers are transferred into their related registers when SIdleAck signal is asserted.

    Did I understood right , that SIdleAck signal is asserted, when the EMIF module goes into idle mode?

    I did try to put the EMIF module into Idle mode. I did try to get it out of that Idle mode, and nothing was transferred  somewhere.

    When that SIdleAck signal is asserted? Or in other words, when the shadow registers are transferred into their related registers? Which bits should be asserted to do this?

     

     

  • 0 in reply to Alexey Govorukhin
    Prodigy 180 points

    Hey, people!!!

    I found it out!!!

     

    There is a one small bit in SDRAM_REF_CTRL Register > REG_INITREF_DIS

     

    This bit should be CLEARED for the start of initialization of EMIF and for the reset of EMIF,

    and it should be SET after setting ALL registers of EMIF. In other words it should be the last bit to set in whole init sequence

    That's all

     

  • 0 in reply to Alexey Govorukhin
    Prodigy 130 points

    Hi Alexey

    From further discussions we've been having on this and some experimentation, the reference code is correct in terms of sequence. We found that setting the initref last stopped our initialisation from working corectly. For the VTP, the sequence that James outlines works as well.

    Our confusion was to do with where we should insert the VTP and how everything fits together as the sequence at the moment is documented in different sources (Code, TRM, Wiki).

    Regards

    Andy

  • 0 in reply to Andy Jump53114
    TI__Guru* 87850 points

    Thanks for the confirmation.

    I added the sequence to the wiki.  We'll get it VTP into a future release of the SDK.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 210 points

    Could you provide the link to the wiki page, please?