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RTOS/DRA71: DDR Cache

user5183370
Intellectual 510 points
Part Number: DRA71

Tool/software: TI-RTOS

Hi

    We now meet a probleam, about the memory shared between M4 & A15.

   M4 get a video frame and save it into DDR, then A15 read the frame from DDR.

   The probleam is that the data in the frame reading from A15 is different from the data in the same fame which M4 captured.

   The memeory in M4 is L1 cacahed & L2 non cached.

   We may suspectted that is the cache probleam,  we had change that the memory in A15 to non cached ,but the difference is sitll on.

  Please help analyze.

 Thx.

  

  

 

  • 0
    TI__Guru 55685 points
    Hi,

    You need to do a cache write back on M4 to make sure data in DDR is consistent.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 510 points
    Hi
    All operations in M4 is based on DMA. Also ,we had do the write back opertaion.

    It's still error.
  • 0 in reply to user5183370
    TI__Guru 55685 points
    Hi,

    M4 has an unicache, L1 and L2 cache are not separate.
    Can you check your implementation as original question says "M4 is L1 cacahed & L2 non cached".
    Also A15 has two levels of cache.
    Can you check if you are disabling both.

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 510 points
    Hi
    1. The configure file in M4 is as bellow:

    AMMU.largePages[1].pageEnabled = AMMU.Enable_YES;
    AMMU.largePages[1].logicalAddress = 0x80000000;
    AMMU.largePages[1].translatedAddress = 0x80000000;
    AMMU.largePages[1].translationEnabled = AMMU.Enable_YES;
    AMMU.largePages[1].size = AMMU.Large_512M;
    AMMU.largePages[1].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
    AMMU.largePages[1].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
    AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
    AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_POSTED;
    AMMU.largePages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    AMMU.largePages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;

    2. In A15 , the DDR physical address will be mapped through CMEM .
  • 0 in reply to user5183370
    TI__Guru 55685 points
    Hi,

    Can you make below change in AMMU mapping and try:
    AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE;

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points
    Hi,

    I haven't heard back from you, I'm assuming you were able to resolve your issue.
    If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

    Regards,
    Rishabh
  • 0 in reply to Rishabh Garg
    Intellectual 510 points
    Hi

    Sorry for not responding in time.
    After we made teh below change in AMMU mapping < AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_NON_CACHEABLE.>
    The M4 can not boot up.
    So we want to learn what the difference between L1 & L2 in the cfg files?

    AMMU.largePages[1].L1_writePolicy = AMMU.WritePolicy_WRITE_BACK;
    AMMU.largePages[1].L1_allocate = AMMU.AllocatePolicy_ALLOCATE;
    AMMU.largePages[1].L1_cacheable = AMMU.CachePolicy_CACHEABLE;
    AMMU.largePages[1].L1_posted = AMMU.PostedPolicy_POSTED;
    AMMU.largePages[1].L2_cacheable = AMMU.CachePolicy_NON_CACHEABLE;
    AMMU.largePages[1].L2_posted = AMMU.PostedPolicy_NON_POSTED;
  • 0 in reply to user5183370
    TI__Guru 55685 points

    Hi,

    As I told previously M4 has a unicache, there is no separate L1/L2 cache. You can remove L2 statements from the code.

    Are you still facing cache issues?

    Regards,

    Rishabh

  • 0 in reply to Rishabh Garg
    TI__Guru 55685 points
    Hi,

    I haven't heard back from you, I'm assuming you were able to resolve your issue.
    If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

    Regards,
    Rishabh