TMS320C6678: TMS320c6678: Cache, MSMC

Surya Paruchuri

Part Number: TMS320C6678

Hello,

I am a little confused by TI's terminology in the datasheet. Could some please clarify the following quick questions. Thank you in advance for the assistance.

1. Datasheet says under features: 32KB L1 Program Per Core, 32KB L1 Data Per Core. 512KB L2 per Core. I am assuming that they are referring to caches' in this context. Is this Correct..?

2. 4096KB MultiCore shared Memory. I am assuming that this corresponds to L-3 Cache. Am I correct...?

Please advice. Thank you.

over 7 years ago

0 Surya Paruchuri over 7 years ago

Intellectual 650 points

1. The data sheet mentions uses Cache later-on in the documentation. (First Question is resolved).

Ty.

0 Yordan Kovachev over 7 years ago

TI__Guru**** 161600 points

Hi,

1. Yes, these are L1P, L1D and L2 caches.

2. This is an SRAM Memory Shared by the DSPs.

Best Regards,
Yordan

0 Surya Paruchuri over 7 years ago in reply to Yordan Kovachev

Intellectual 650 points

Hi Yordan. Thanks for the reply.

2. So this is not a cache, but an actual memory (RAM) itself used for storage in addition to DRAM.? If yes doesn't keystone architecture have L-3 shared Cache..? Is L-2 the last level of cache in the architecture. (specifically C6678)..? If so, is CSL's cache library meant only for L-1D/P and L-2 caches..? Please advice. TY.

0 Yordan Kovachev over 7 years ago in reply to Surya Paruchuri

TI__Guru**** 161600 points

Hi,

This is explained in the Datasheet, section 5.1 Memory Architecture. There are the following onchip memories:
L1D, L1P
L2 Memory
MSMC (SRAM) --> which can be configured as shared L2 and/or shared L3 memory
L3 Memory --> This is ROM.

As I said read section 5.1 from the device Datasheet for further details.

Best Regards,
Yordan

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TMS320C6678: TMS320c6678: Cache, MSMC