Hello ,
My design requirement is to pass a 1905 X 840 X 30 fps & 16 bit color to the TMS320DM6437ZWTQ5's CCDC.
To make that happen I need a pixel clock (PCLK) frequency of at least 1905 X 840 X 30 fps X 2 = 96.012 MHz.
It seems the TMS320DM6437ZWTQ5 – cannot accept such a high frequency, as described in spru977 at page 81: http://focus.ti.com/lit/ug/spru977d/spru977d.pdf “The video port interface delivers data at a rate independent of the PCLK. By default, this rate is set to DSPCLK/3)/2 (~75 MHz for Normal mode and 99 MHz for Turbo mode), which is fast enough to support a PCLK of ~71 MHz for Normal mode and 90 MHz for Turbo mode) .” Question:
If I swapped TMS320DM6437ZWTQ5 with TMS320DM6437ZWTQ6, which has a clock of 660MHz (as opposed to 500MHZ for Q5), would the CCDC support the 96MHz PCLK, as needed?
According to the formula in spru977d.pdf mentioned above, the PCLK must be lower than (660MHz/3)/2 = 110 MHz, which is
quite a bit higher than 96MHz, and the condition is met.
Thank you,
Chris
