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DRA74: Using PCIe on the J6

Chris Lande
Expert 6060 points

Part Number: DRA74

Hello Support,

We’ve been trying to use the J6 PCIe interface to connect to a WiFi module on our board but we’re having some problems.

Our board is still based on the circuit from the evaluation board, can you tell me if this is intended to work as a PCI endpoint or a PCI host?

The Users Guide suggests that the DRA74x-evm boards are intended to be operated in Root Complex mode. However when we tried we found that we needed to replace the 100R termination resistor (across LJCB_CLKN and LJCB_CLKP) with two 50R resistors, one from each signal to ground. This piece of guesswork was based on a brief trawl of the internet which suggested that we might also need series resistor depending on the internal configuration of the host (J6). Based on this we’d like to know:-

  1. Are our 50R to ground termination resistors OK for the J6?
  2. Our WiFi module is on the same board as the J6; should we place the termination resistors near the module or near the J6?
  3. Should we fit series resistors as well? (And if so what value would be best?)
  4. Are there any other hardware features we should consider for reliable PCIe operation?

Thanks.

  • 0
    TI__Genius 16275 points

    Since your board is based on the evaluation board, can you confirm that you are using the same CDCM9102 dual output clock generator?  If so, then they EVM clock termination scheme should be followed.  Only if you are sourcing the 100MHz directly from J6 (with no CDCM9102) on the board, should the termination scheme me modified to use the dual 50ohm-to-GND resistors.

  • 0 in reply to B.C.
    TI__Expert 6060 points

    The CDCM9102 has been removed from the design. 

    Can you tell me why the clock generator (CDCM9102) was used? i.e. why not source the clock directly from the J6?

    Thanks.

  • 0 in reply to Chris Lande
    TI__Genius 16275 points

    The EVM was designed with population options to support three different clocking modes:

    - CDCM9102 provides 100MHz Refclk to both J6 and the PCIe connector (default population option that matches traditional PC motherboard implementation)

    - J6 provides 100MHz Refclk directly to the PCIe connector

    - J6 accepts 100MHz Refclk from the PCIe connector

    Section "LJCB_REFN/P Connections" of the datasheet describes termination requirements in Output REFCLK mode which you are using on your board.

    Are you seeing a clock output on the LJCB_REFN/P pins?  It must be present before releasing reset to the PCIe Link Partner (Wifi chip).

  • 0 in reply to B.C.
    TI__Mastermind 42515 points
    Hi Chris,

    We haven't heard back from you, I'm assuming your questions has been answered.
    If not, just post a reply below (or create a new thread if the thread has locked due to time-out).

    Regards,
    Yordan