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TMS320C6657: PCIe Legacy INTA

Part Number: TMS320C6657
Other Parts Discussed in Thread: SYSBIOS

Hi, 

My issue is related to PCIe Legacy INTA  configuration.

Setup :

I am using the DSP as a RC and FPGA as  an EP device.

The wiki page  "Configuring interupts on keystone devices" states that there is two ways to go about doing that, the first being through CSL-API or SYS/BIOS.

Using the CSL approuch  i could successfully activate the Legacy INTA and will call my ISR function when an interrupt occurs. But on the otherhand  all configured  created clocks  using SYS/BIOS that call functions  periodically  and tasks stopped working.

I have read in one thread that one should not use both SYS/BIOS and CSL API  simultaneously , so i tried using the SYS/BIOS approach , but  for some reason my ISR is never being  called. 

CSL-API approach:

DEVICE_REG32_W(PCIE_LEGACY_A_IRQ_STATUS, 0x1); // clear status


intcContext.eventhandlerRecord = EventHandler;
intcContext.numEvtEntries = 2;
CSL_intcInit(&intcContext);
if (CSL_intcInit(&intcContext) != CSL_SOK)
{
printf("Error: GEM-INTC initialization failed n\r");

}

/* Enable NMIs */
if ( CSL_intcGlobalNmiEnable() != CSL_SOK)
{
printf("Error: GEM-INTC global NMI enable failed n\r");

}

/* Enable global interrupts */
if ( CSL_intcGlobalEnable(&state) != CSL_SOK)
{
printf("Error: GEM-INTC global enable failed \n\r");

}

vectId=CSL_INTC_VECTID_4;
int eventId = 25;

hTest = CSL_intcOpen (&intcObj, eventId, &vectId, NULL);
if (hTest == NULL)
{
printf("Error: GEM-INTC Open failed\n\r");

}

/* Register an call-back handler which is invoked when the event occurs. */
EventRecord.handler = &test_isr_handler;
EventRecord.arg = (void *)eventId;
if (CSL_intcPlugEventHandler(hTest, &EventRecord) != CSL_SOK)
{
printf("Error: GEM-INTC Plug event handler failed\n\r");

}

/* Clear the event in case it is pending */
if (CSL_intcHwControl(hTest, CSL_INTC_CMD_EVTCLEAR, NULL)!= CSL_SOK)
{
printf("Error: clearing pending event failed\n\r");


}
/* Enable event */
if (CSL_intcHwControl(hTest, CSL_INTC_CMD_EVTENABLE, NULL)!= CSL_SOK)
{
printf("Error: GEM-INTC CSL_INTC_CMD_EVTENABLE command failed\n\r");
}
/*** --- CIC Initializations --- ***/

hnd = CSL_CPINTC_open(0);
if (hnd == 0)
{
printf("Error: Unable to open CPINTC-0\n\r");

}


CSL_CPINTC_disableAllHostInterrupt(hnd);

CSL_CPINTC_setNestingMode (hnd, CPINTC_NO_NESTING);

CSL_CPINTC_clearSysInterrupt (hnd, 50);

CSL_CPINTC_enableSysInterrupt (hnd, 50);

CSL_CPINTC_mapSystemIntrToChannel (hnd, 50, 3);

CSL_CPINTC_enableHostInterrupt (hnd, 3);

CSL_CPINTC_enableAllHostInterrupt(hnd);
LEGACY_A_IRQ_ENABLE_SET=0x1;

static void test_isr_handler(void* handle)
{
counter++;

CSL_CPINTC_disableHostInterrupt (hnd, 3);
/* clear PCIE interrupt */
DEVICE_REG32_W(PCIE_LEGACY_A_IRQ_STATUS, 0x1);
DEVICE_REG32_W(PCIE_IRQ_EOI, 0x0);
 CSL_CPINTC_clearSysInterrupt (hnd, 50);
/* Enable host interrupt */
CSL_CPINTC_enableHostInterrupt (hnd, 3);

printf("INT CNT %d \n",counter);

}

SYS/BIOS approach:

DEVICE_REG32_W(PCIE_LEGACY_A_IRQ_STATUS, 0x1);
//Map secondary inputs to the Core event
CpIntc_mapSysIntToHostInt(0, 50, 3);
CpIntc_dispatchPlug(50,(CpIntc_FuncPtr)test_isr2_handler, 50, TRUE);

CpIntc_enableHostInt(0, 3);
CpIntc_enableSysInt(0, 50);
int eventId = CpIntc_getEventId(3);

Hwi_Params hwi0Params;
Hwi_Params_init(&hwi0Params);
hwi0Params.arg = 3;
hwi0Params.eventId = eventId;
hwi0Params.enableInt = TRUE;

Hwi_create(4,&CpIntc_dispatch, &hwi0Params, NULL);
Hwi_enableInterrupt(4);

Hwi_enable();

LEGACY_A_IRQ_ENABLE_SET=0x1;

 

static void test_isr2_handler(void* handle)

{

counter++;

CpIntc_disableHostInt(0, 3);

/* clear PCIE interrupt */

DEVICE_REG32_W(PCIE_LEGACY_A_IRQ_STATUS, 0x1);

DEVICE_REG32_W(PCIE_IRQ_EOI, 0x0);

CpIntc_clearSysInt(0, 50);

/* Enable host interrupt */

CpIntc_enableHostInt(0, 3);

printf("INT CNT %d \n",counter);

}

 Questions:

1) Can I configure  different components using  both CSL -API and SYS/BIOS simultateously?

2) What can be the reason why using CSL approach for configuring legacy INTA works but not with SYS/BIOS approach ? Am i missing something ?

N.B i am using the link " processors.wiki.ti.com/.../Configuring_Interrupts_on_Keystone_Devices" as my reference.

3) In the. cfg file i have only the following defined  var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc')  do  I need to add something else?

Best Regards,

Hisham

  • Hi Hisha,

    Take a look at the Processor SDK RTOS PCIe examples:
    software-dl.ti.com/.../Device_Drivers.html

    You can see how interrupts are handled there.

    Best Regards,
    Yordan
  • Hi Yordan,

    Thanks for the link, but I could not find an example that uses the Legacy interrupt mode  for PCIe  and where the interrupts are configured using hwi and CpInt to create and map  a system interrupt to host interrupt.

    From the wiki page the following is mentioned which answers my first question.

    "If application developers plan to use SYS/BIOS RTOS on their device, then it is recommended that they leverage the relevant SYS/BIOS Interrupt APIs to configure interrupts, and use CSL APIs only where an equivalent function does not exist in the SYS/BIOS APIs. However, here it is important to note that if application developers use both SYS/BIOS and CSL APIs for the purpose of mapping interrupts and writing to the Interrupt Service Table Pointer (ISTP), there will be conflicts since both CSL and SYS/BIOS will assume that they own ISTP."

    Can this be an explanation why using the CSL-API works, but results in other hwis configured using sys/bios to stop working?

    Is there anything wrong with my SYS/BIOS approach that i provided? If not how can further debug my problem?

    Thank you in advance,

    Hisham 

  • Hi,

    Sorry for the delayed reply. Did you configure the interrupts in the .cfg file of your project.
    See:
    processors.wiki.ti.com/.../Configuring_Interrupts_on_Keystone_Devices

    Best Regards,
    Yordan