Other Parts Discussed in Thread: OMAP3530
The Figure 12-6. SYNC Mode Clock Gating in the OMAP3530 TRM describes the requirement of 4 advanced pixel clock input before start of frame.
Is this 4 pulses required for the initialization of the serial receive circuit ?
If the 4 pulses of the pixel clock were not inputted before start of frame, the 1st frame data will not be captured?
And if another 4 pulses of the pixel clock were also missed before start of the 2nd frame, the 2nd frame data will not be captured again ?
Is this requirement needed for any SYNC mode receive communication on the ISP ?
Thanks and Best Regards,
KIMIZUKA