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AM3352: UART receive data loss

Guru 10105 points
Part Number: AM3352
Other Parts Discussed in Thread: AM3358, TMDXEVM3358

Hi Sitara support team,

There is the following issue in AM335x UART receiving processing.

Environment:
-Custome board using AM3352
-Customized Linux SDKv4
-Application:
Sending 51 bytes of data from the PC.
(The data is serial number 0x10 to 0x42, meaningless for the data itself)
Receiving with custom board.

Result:
Normal state: Received 51 bytes, no problem with data.

Error state1: Received processing ends with 50 bytes.
When checking the data, 0x41 is missing. (50th byte)

Error state2: It receives 51 bytes, but 0x41 is missing.
And a data not transmitted from PC is included in 51st byte.


From the driver processing, it seems that "48 bytes" are set as an interrupt trigger at the receiving,
RHR is read during an interrupt processing, and it is judged whether to continue reading
by checking RX FIFO of LSR_UART.

Question:
Is there information on the cause and measures about this issue that data is lost at the interrupt timing?

Best regards,
Kanae

  • Hi Kanae,

    TI Processor SDK v4 has multiple releases, which one do you use?

    Does your kernel use 8250_omap driver, not omap_serial?

    If you use 8250_omap, does the issue still happen if disable DMA for 8250_omap driver?

    In kernel manuconfig:

    Device Drivers >
        Character devices >
            Serial drivers >
                8250/16550 and compatible serial support >
                    DMA support for 16550 compatible UART controllers
    
  • Hi Liu,

    Thank you for your reply.

    I have checked the driver information to my customer that uses " 8250_omap driver".
    When it sets disable DMA support, but it still occurs the error.

    Here are the additional information from my customer.

    *****************************************************************************************

    Occurrence frequency: in about 2000 trials

    Error state 1: about 1,200 times

    Error state 2: about 40 times.

     

    Environment :

    AM3352 custom board

    Customized Linux OS

     

    When it is checked using TI AM335xEVM just 50 trials, there is no error.

    When they changed to the wait time of the process of reading data from FIFO,

    there is no error at all.

    *****************************************************************************************

     

    Question:

    My customer do not know the cause, so they cannot judge whether it is a appropriate measure, or not.

    Could you please tell me the cause and the appropriate measure?

    From your experience, If you have the detailed information such as how much should it be added the wait,

    it really would be appreciated.

     

    Best regards,

    Kanae

  • Kanae,

    Kanae said:
    Occurrence frequency: in about 2000 trials

    What occurs in about 2000 trials?

    Kanae said:
    Customized Linux OS

    What version of the Processor SDK kernel is the customized Linux based on? What the customization is? Is the kernel modified?

    Kanae said:
    When it is checked using TI AM335xEVM just 50 trials, there is no error.

    Is the 50-trails test long enough? Can you please test it longer? What kernel do you use when testing on the TI EVM?

    Which uart port is used in your custom board? and which port you tested on the TI AM335x EVM?

    Kanae said:

    Could you please tell me the cause and the appropriate measure?

    From your experience, If you have the detailed information such as how much should it be added the wait,

    I still need more information to understand the issue. Please answer my questions above.

  • Hi Liu,

    Thank you very much for your support.

    Regarding Occurrence frequency, I change to the expression as following.

    Occurrence frequency:
    -Error state 1*: about 1,200 times occurrence in about 2000 test trials
                     (about 60%)
    *Error state1: Received processing ends with 50 bytes. When checking the data, 0x41 is missing. (50th byte)


    -Error state 2**: about 40 times occurrence in about 2000 test trials       
                     (about 2%)
    **Error state2: It receives 51 bytes, but 0x41 is missing. And a data not transmitted from PC is included in 51st byte.

     

    I have asked some of your questions to my customer.
    I will have the information you asked, and report them to you later.

    Best regards,
    Kanae

  • Kanae,

    Thanks for the clarification. Now I understand the test does 2000 iterations, Error 1 happens in about 1200 iterations, and Error 2 happens in about 40 iterations.

    Waiting for your further information.
  • Hi Hanae,

    I haven’t heard back from you, I’m assuming you were able to resolve your issue. If not, just post a reply below (or create a new thread if the thread has locked due to time-out). thanks.
  • Hi Liu,

    I am sorry for my late reply.
    My customer did not give us their reply yet.
    I will check their status and post it later.

    Best regards,
    Kanae
  • Hi Liu,

    I have got customer's answers as follows.

    -What version of the Processor SDK kernel is the customized Linux based on?

    A1. Using SDKv4.3 and kernel version 4.9.69

     

    -What the customization is? Is the kernel modified?

    A2. On custom board, RS485 is mounted and it is modified to control GPIO at switching the RTS

       by driver in order to control transmission / reception with GPIO.

     

    -Is the 50-trails test long enough? Can you please test it longer?

    -What kernel do you use when testing on the TI EVM?

    A3. They did the additional test with AM335x StarterKit at 2000 times and there is no error.

     

    -Which uart port is used in your custom board? and which port you tested on the TI AM335x EVM?

    A4. Starter kit: UART5

        Custom board: UART5

     

    Result of their investigation;

    - They have found that this error status seems to be caused by clearing the RX FIFO at an unintended timing.

    - Their board uses half-duplex RS485 and it seems to clear the FIFO at the transmission stop processing

     if the driver is set the half-duplex RS485.

     

    Current measures;

    - If the interruption processing is a reception related interrupt, the transmission related processing is not executed.

    - When it is operating with RS485, it does not call the flush processing called from serial_core.c.

     

    They are planning to deal with it in above measures.

    Is there any notes for the software during operating with half-duplex RS485?

     

    Best regards,

    Kanae

  • Kanae,

    Why and how your customer uses GPIO to control the RTS? It does sound like sw timing issue which causes RX FIFO flush too soon.
    The AM335x SK UART5 is not configured by default, how did your customer test the same RS485 on the SK board? the board and sw are modified?

  • Hi Liu,

    I was wrong the TI EVM name that my customer use.
    They use TMDXEVM3358, not AM3358_StarterKit.
    Sorry for making you confused.

    >Why and how your customer uses GPIO to control the RTS?

    In the status of UART driver initialization, RTS becomes HI,
    but their board is "HI = transmission mode", so they decided to control with GPIO
    so that it will not be in unintended transmission mode.


    >It does sound like sw timing issue which causes RX FIFO flush too soon.

    → The RX FIFO flush is performed by the original driver,
    but is it possible to fix the software to delay this?

    Although they are considering to avoid calling the flushing process
    as described "Current measures" in last my post,
    is there any possibility that other problems may occur by avoiding calling flush?

    Best regards,
    Kanae

  • Hi Liu,

    Could you please reply any your comments to the customer's current measures?

    Best regards,
    kanae
  • Kanae,

    I am trying to understand why CTS is high after init, or if possible to change in sw. Please give me some time to look at this.

    Meanwhile, can you please ask your customer if they did apple-to-apple comparison on their board and AM335x EVM, for example, GPIO controlling RTS, and RS-485 transfer? Because I am not sure how their test was done on the AM335x EVM, which doesn't have UART5 enabled by default, and doesn't have RS-485 on the EVM.

  • Hi Kanae,

    Kanae said:
    In the status of UART driver initialization, RTS becomes HI,
    but their board is "HI = transmission mode", so they decided to control with GPIO
    so that it will not be in unintended transmission mode.

    GPIO should not be used to control the rs485 transceiver, it adds the flow control complicity into the software.

    The UART RTS level for idle or active state can be controlled using the flags defined in user space application. Please check the example code in the kernel documentation:

    Documentation/serial/serial-rs485.txt

  • Kanae,

    I noticed you posted a new question regarding transmission data loss, is this issue solved?
  • Hi Bin Liu,

    I am sorry my reply is late.

    Here is how their test was done on the AM335x EVM.

    UART5 was enabled by the following procedure.
    ・ Replace with DTB which is enabled UART5.
    ・ Operate DipSw for CPLD and select Profile #6

    The RS485 transceiver is not connected, but my customer judged that it is no problem
    even if checking with EVM's "RS232".
    Because the problem transmission data missing is no data transmission from the AM 3352.


    Regarding the solution, they have just kept their own measure posted on Oct-1st.

    Best regards,
    Kanae

  • Hi Kanae,

    Please let me know if the issue is solved with the following kernel patch you found in the community?

    e2e.ti.com/.../2730218
  • Hi Bin Liu,

    Customer reported that the kernel patch does not work to the receiving data loss issue.

    The reproducibility is at about the same ratio without the patch.
    However, the following customer's measure works to the issue
    and there is no reproducibility at 40000 times tests.

    *This customer's investigation and the measure are posted Oct-1st in this thread.*

    Result of their investigation;
    - They have found that this error status seems to be caused by clearing the RX FIFO at an unintended timing.
    - Their board uses half-duplex RS485 and it seems to clear the FIFO at the transmission stop processing
     if the driver is set the half-duplex RS485.

    Current measures;
    - If the interruption processing is a reception related interrupt, the transmission related processing is not executed.
    - When it is operating with RS485, it does not call the flush processing called from serial_core.c.


    **********************************************************************************************
    [Customer view of this patch for the receiving data loss issue]

    The received data loss is occurred the following mechanism.

    When the receiving data equal to or greater than the number of bytes set in the interrupt trigger,
    the receiving data cannot be read by the driver's interrupt processing.
    And then FIFO clear processing is called so that a few bytes disappear which the number of bytes
    after setting in the trigger.

    [Example]
    Transmitting 51 bytes from PC
    → receiving on AM 3352 board and generating an interrupt when 48 bytes (initial value) is into the FIFO
    → reading 48 to 49 bytes by interrupt processing
    → the interrupt processing has done since both RXFIFOE and RXBI of LSR are "0"
    → FIFO clear processing runs around 50th bytes into FIFO
    → "50th byte" disappears

    Therefore, the patch does not perform "unnecessary register operation in FIFO clear processing"
    customer thinks that the patch has no effect on the received data loss.
    **********************************************************************************************


    They are planning to deal with it in above their current measures.
    Is there any notes for the software during operating with half-duplex RS485?

    Best regards,
    Kanae