I realize this isn't a C6000 issue, however there is no C40 forum.
Can someone please comment on the issue we are seeing below?
The TMS320C40 appears to have a limitation as to when interrupts are actually disabled in response to clearing the Global Interrupt Enable (GIE) in the processor’s Status register (ST). Through the use of logic analyzer traces of code execution along with instrumented code it has been observed that the C40 will allow an interrupt to occur (and code execution to be directed to the associated interrupt service routine) several instruction after interrupts are disabled (GIE=0). There does not appear to be any such limitation called out in the TMS320C4x User’s Guide. Our code currently uses the following assembly language instruction to disable interrupts in the C40:
ANDN 2000H,ST ; disable GIE
The Bitwise logical-AND with complement should result in zeroing the GIE (bit 12) in the ST.
Unsuccessful Attempted Workarounds:
After discovering the above reported problem several variants of the above code have been tried including:
; adding one or more NOP instructions following the disabling of interrupts
ANDN 2000H,ST ; disable GIE
NOP
NOP
;using a delay branch instruction which per its description guarantees that the three instructions following it cannot be interrupted
BRD lb1
ANDN 2000H,ST ; disable GIE
NOP
NOP
lb1:
;using a delay branch instruction and then immediately reading back the ST
BRD lb1
ANDN 2000H,ST ; disable GIE
STI ST,@Saved_STReg ; read back and save ST in global RAM location
NOP
lb1:
In each of the above cases we have found that we are still able to take an interrupt at least one of more instructions after these code sequences. As a point of interest in the case of this last code sequence we were able to show from the interrupts service routine that preempted this code sequence that the Saved_STReg showed that the GIE was actually 0 indicating interrupts should have been disabled.