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DDR2 external probe gating

cobsonchael
Mastermind 7930 points

We are designing a project using the C6748. I see in one of the options in the DDR2 ap-note is internal or external probe gating (found in the DRPYC1R register in the doc sprugj4.pdf).  I cannot find anywhere what that means. that was not an option for the 6421 DSP we used before so I/we are kind of lost on this. any help?

  • 0
    Mastermind 7930 points

    or strobe gating. oops

  • 0
    Expert 2270 points

    I would like to know about External DQS Strobe Gating on the 674x too.

    In the memory controller user's guide the powerup initialization procedure has a step to set EXT_STRBEN to 1 to selected external strobe gating.

    Configure the DDR PHY control register 1 (DRPYC1R). All of the following steps may be done in a
    single register write to DRPYC1R.
    a. Set the EXT_STRBEN bit to 1 to select external DQS strobe gating.
    b. Program the RL bit to the required value

    Does this mean it should always be set to 1?

    Thanks!

    CJ