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AM3358: DDR3 data signal problem

Bart
Expert 6460 points
Part Number: AM3358

Dear Team,

our customer has problems with the shapes of the signals on the data traces (using AM3358BZCZA100 and MT41K256M16TW memory).

The signals have been captured with an oscilloscope and analyzed. We have a written report and the design files that we would like to share offline.

With whom may we contact to analyze it?

Thank you,
Kind regards

  • 0
    TI__Guru* 87400 points

    Response via email

    —james

  • 0 in reply to JJD
    TI__Guru* 87400 points
    Bartosz, I received the files. Are there specific question from the customer?

    I see their kernel boot is failing. After a failed boot, can the break in to the processor with JTAG and use CCS to look at the DDR memory region to see if it is stable?

    Thanks,
    James
  • 0 in reply to JJD
    TI__Expert 6460 points
    Hi James,

    customer would like to know if the design will be OK or not, do you see any issues or have any remarks about it?

    Regarding the kernel boot failing, we will check your recommendation. Now we are facing this kernel-panic situation, but we do not know exactly, if this is a real hardware problem or something else (e.g. wrong settings in the kernel). We wrote a hw-tester and used to test the DDR memory script (included in the gel file) in the CCS, but never saw any problems.

    Looking forward for your feedback and thank you.
    Bartosz
  • 0 in reply to Bart
    TI__Expert 6460 points

    Hi James,

    to recap: "our DDR design is quite the same as the AM335x Starter Kit, impedance controlled signals (75 Ohm), matched length traces with termination resistor on address lines with the Vtt regulator. 

    I checked the signals with 8GHz scope on the address lines and on the data lines. I would say the signals on the address bus are OK and if the Sitara processor drive the data bus it will be OK too, but if the DDR memory drives the data lines, the signals will get some extra peaks due to the reflexion. However the AM335x DDR Tests which is integrated to the gel file were passed.

     

    I started with editing our gel file especially the SDRAM_CONFIG register to determinate the drive strength value and DDR termination value. My feeling is that there was no any effect on the DDR side. We try to find how to change these values and we learned it is could be set through the Mode Register 1 (MR1) according to the DDR datasheet. Is there any possibility to check these values during the DDR initialization?

    I checked the DDR datalines on Beaglebone Black with its gel file, and the result was the same as you can see below.

    • Could you please help clarifying it?

    Thank you.

  • 0 in reply to Bart
    TI__Guru* 87400 points
    Hi Bartosz, it is difficult to tell if you are going to have issues just by looking at these shots. A lot depends on where along the trace you probed.
    Note that the tests provided by the GEL scripts are just rudimentary tests that perform basic read/write tests to the memory. It is up to the customer to create stress tests based on his design to truly test the interface. We typically use a test called memtester in the linux kernel to do more bandwidth intensive tests.

    During initialization, the DDR controller will initialize the MR registers in the DDR. The settings in the SDRAM_CONFIG register will get written to the DDR during initialization. There is no way to verify the writes to the MR, as there is no way to read the MR registers in the memory. You should see signaling differences during a read when adjust the parameters in the SDRAM_CONFIG register, especially ddr_term and sdram_drive.

    Regards,
    James