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RTOS/AM5746: Memory allocation

Guru 24520 points
Part Number: AM5746
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hi TI Experts,

Please let me confirm the following question.

[Question]
Would you please teach me the way to specify the memory address like OCM or DDR to be used for each core?

Best regards.
Kaka

  • The RTOS team have been notified. They will respond here.
  • Hi,

    If your use bare metal, it is straightforward you can edit the linker command file, to define several non-overlap regions for OCMC and DDR, then core 0 program use some regions and core 1 use the others.

    If you use SYSBIOS, let you check how to do this.

    Regards, Eric
  • Hi

    My customer will use the TI-RTOS. So, which document should customer check?

    Best regards.
    Kaka
  • Hi,

    I will find this info and let you know.

    Regards, Eric
  • Thank you for your support.
    I am waiting for your update.

    Best regards.
    kaka
  • Kaka,

    When you want to split the memory for each core, I assumed that you want to run different programs in each. If you run the cores in SMP, you don't need to do this.

    Below is an example how we did this:

    our IPC examples append “ipu1-0” and “ipu1-1” to the evmDRA7XX platform:

    C:\ti\am57xx-5.1\ipc_3_50_01_01\examples\DRA7XX_bios_elf\ex02_messageq\shared\Config.bld:

    Build.platformTable["ti.platforms.evmDRA7XX:ipu1-0"] = {

       externalMemoryMap: [

           [ "IPU1_0_PROG", {

               name: "IPU1_0_PROG", space: "code/data", access: "RWX",

               base: 0x86000000, len: 0x800000,

               comment: "IPU1-0 Program Memory (8 MB)"

           }],

           [ "SR_0", SR_0 ]

       ],

       codeMemory:  "IPU1_0_PROG",

       dataMemory:  "IPU1_0_PROG",

       stackMemory: "IPU1_0_PROG"

    };

    Build.platformTable["ti.platforms.evmDRA7XX:ipu1-1"] = {

       externalMemoryMap: [

           [ "IPU1_1_PROG", {

               name: "IPU1_1_PROG", space: "code/data", access: "RWX",

               base: 0x86800000, len: 0x800000,

               comment: "IPU1-1 Program Memory (8 MB)"

           }],

           [ "SR_0", SR_0 ]

       ],

       codeMemory:  "IPU1_1_PROG",

       dataMemory:  "IPU1_1_PROG",

       stackMemory: "IPU1_1_PROG"

    };

    And then we change the platform in CCS:

    You can apply the same idea to A15.

    Regards, Eric

  • Hi Eric,

    Thank you for your confirming.
    To summary your comments, customer can manage the memory to separate the memory address by each cores by making the platform library via bld file. Right?

    Also, did you have IPU example working on CCS? If yes, would you please share with it?
    I could not found it on the SDK including the IPU package..

    Best regards.
    Kaka
  • Hi,

    "To summary your comments, customer can manage the memory to separate the memory address by each cores by making the platform library via bld file. Right?" Yes, this is right.

    "Also, did you have IPU example working on CCS? If yes, would you please share with it?"
    Almost all driver examples has IPU support, like A15 and C66x. You can use pdkprojectcreate to create a driver example for M4, then you will get a CCS project to build and run. Note the driver examples use single core, no matter A15, or C66x or M4.

    If you are looking for SMP examples for M4, the only one we have is POSIX SMP example, which I am confirming with dev team how to test and run, the user guide has no such info.

    Regards, Eric
  • Hi,

    I confirmed that SMP is also supported on M4, I updated e2e.ti.com/.../729224.

    Regards, Eric