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720p h.264 encoding with reduced frequency?

MW51194
Intellectual 855 points

Hello,

 

on the evmdm365 board I have to reduce the PLL1 output for SYSCLK4 from 121.5 MHz (default)  to 108 MHz because I need a unique frequency on the SPI interface. Unfortunately, this is the clock for EDMA and the other peripherals too. The datasheet of the DM365 says, that this clock should be half of the SYSCLK3 (HDVICP bus interface clock) value so I have to reduce that clock too (from 243 MHz (default) to 216 MHz). What will be the performance loss of that reduction? Can I still encode 720P video with H.264 codec?

 

Regards

  • 0
    TI__Genius 9490 points

    MW,

    Good question on the performance reduction, from the HW perspective it is probably hard to quantify how the encoding capabilities are impacted, so maybe someone in the multimedia codecs forum might have a better idea. (i'll move the thread to that forum so codec experts can comment) 

    One minor suggestion from the HW perspective is to try to avoid this PLL CLK change would be to use the SPI4 instance (if the pins are available in your system) this is the only SPI instance that can run from a different Clock independent of the PLLC1.SYSCLK4 clk. Keep in mind that the SPI4 has some limitations like it has not interrupt or EDMA support and also when used in Slave mode it does not support chip select input signals.

    regards,

    miguel

     

  • 0 in reply to Miguel A. Alanis
    Intellectual 855 points

    Hello,

     

    I need a 54 MHz clk on the SPI module. I think, the SPI4 is clocked by the oscillator pins (MXI and MXO with max. 36 MHz) so unfortunately I can't use it. Or is there an external clk input for the SPI4 clock?

     

    What if I use the MJCP / HDVICP bus interface clock with 270 MHz and the EDMA clock with 108 MHz? Is this constellation possible?

     

    Regards,

     

    Matthias

  • 0 in reply to MW51194
    TI__Genius 9490 points

    Matthias,

    Unfortunately the maximum SPI clock supported on dm36x devices is 40Mhz as stated in the datasheet's section 6.15.2 SPI Electrical Data/Timing, so you will be running out of spec even if you could.

    There is no external clk input for the SPI4 clk by the way.

    regards,

    miguel