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AM4378: Multiple NAND devices

AnBer
Mastermind 30120 points
Part Number: AM4378

Team,

Regarding using GPMC for NAND:

I assume that it is possible to use multiple NAND devices on the GPMC.
-Are there some restriction on which GPMC_CSNx should be used when multiple NAND need to be used?
-Is there an ECC module present for every CSN memory space? or is there one single ECC module for the entire GPMC?
-Are the SW drivers (Linux, RTOS) supporting multiple NAND devices interfaced on the GPMC?

Thanks in advance,

Anthony

  • 0
    TI__Guru**** 393215 points

    Anthony,

    AnBer said:
    -Are there some restriction on which GPMC_CSNx should be used when multiple NAND need to be used?

    The only restriction would be the total load capacitance presented on the GPMC bus. It should not exceed device specs.

    AnBer said:
    -Is there an ECC module present for every CSN memory space? or is there one single ECC module for the entire GPMC?

    There is only one ELM module.

    AnBer said:
    -Are the SW drivers (Linux, RTOS) supporting multiple NAND devices interfaced on the GPMC?

    I don't understand the meaning of this. You can instantiate the available NAND driver as necessary.

  • 0 in reply to Biser Gatchev-XID
    TI__Mastermind 30120 points

    Hi Biser,

    Biser Gatchev-XID said:
    AnBer
    -Are there some restriction on which GPMC_CSNx should be used when multiple NAND need to be used?

    The only restriction would be the total load capacitance presented on the GPMC bus. It should not exceed device specs.

    From your experience can the GPMC IO supports 1x NOR and 2x NAND (ie in total 3 chips)?
    I know that it depends on the specific NOR/NAND GPIO specs and on the PCB design but generally speaking have you seen this config working on some Sitara designs?

    Also I understand that only one Flash can be used for boot (as GPMC boot is only on CSN0).

    Biser Gatchev-XID said:
    AnBer
    -Are the SW drivers (Linux, RTOS) supporting multiple NAND devices interfaced on the GPMC?

    I don't understand the meaning of this. You can instantiate the available NAND driver as necessary.

    If there is only one ELM then it needs to be share in case 2 NANDs are hooked to the GPMC. This means that the the driver need to maintain 2 config/data table (one for each NAND).
    -Is the Linux drivers supporting multiple NAND (in the devicetree to define multiple NAND, in the kernel driver to keep multiple config at run time and at the application level to access both memory area)?
    -Has this been tested as part of the Linux SDK testing?

    Thanks in advance,

    Anthony

  • 0 in reply to AnBer
    TI__Guru**** 393215 points

    AnBer said:
    From your experience can the GPMC IO supports 1x NOR and 2x NAND (ie in total 3 chips)? I know that it depends on the specific NOR/NAND GPIO specs and on the PCB design but generally speaking have you seen this config working on some Sitara designs?

    I have seen forum users comment on using 2 or 3 NANDs, I can't remember exactly.

    As for the Linux questions, I have asked the SW team to comment.

  • 0 in reply to Biser Gatchev-XID
    TI__Mastermind 26205 points
    Amber,
    sorry for the delay, we are checking this post...
  • 0 in reply to Rogerio Almeida
    TI__Genius 9510 points
    Each NAND should have a unique chip select and each chip select has its own set of registers. GPMC_CONFIGn_m where n is reg7-0 and m is CS[6-0]. The GPMC duplicates its registers for each chip select.

    After configuring two GPMC chip select register sets with the NAND configuration. They are uniquely memory mapped so writing or reading from one GPMC Reg set accesses the first NAND and writing or reading from another address accesses the other NAND. ie GPMC_NAND_COMMAND_m, GPMC_NAND_ADDRESS_m and GPMC_NAND_DATA_m.
  • 0 in reply to Marcus Cooksey
    TI__Mastermind 30120 points

    Hi Marcus,

    Thanks for the answer, it helps.

    But we would need some more information on the SW side. Any input the  SW can provide?

    If there is only one ELM then it needs to be share in case 2 NANDs are hooked to the GPMC. This means that the the driver need to maintain 2 config/data table (one for each NAND).
    -Is the Linux drivers supporting multiple NAND (in the devicetree to define multiple NAND, in the kernel driver to keep multiple config at run time and at the application level to access both memory area)?
    -Has this been tested as part of the Linux SDK testing?


    Thanks in advance,
    Anthony

  • 0 in reply to AnBer
    TI__Genius 9510 points
    We don't support multiple NAND configurations in software, although it should be feasible. However software support for multiple ELMs across 2 NAND devices is even more complex and has never been verified.