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Linux/AM3351: KSZ8863 switch RMII connection

Santhosh Ramani
Expert 2765 points
Part Number: AM3351

Tool/software: Linux

Hi,

We have a custom design with AM3351 and KSZ8863RLL with RMII, used as a ethernet switch. (AM3351 MAC --> PHY KSZ8863). I have few questions:

1. Looking at other forum replies (https://e2e.ti.com/support/processors/f/791/p/649924/2393181#2393181, it seems that the timing is extremely tight for RMII - can you some elaborate the exact parameters that are being compared?

2. We also plan to use ethernet boot during manufacturing - does the ROM boot code support ethernet switch or will it be transparent and be considered as a normal PHY. (assuming the boot strap options for the PHY are setup correctly for operation without modification of internal registers on the PHY)

Thank you

Regards

Santhosh

  • 0
    TI__Mastermind 27890 points
    Hi Santhosh,
    1) Budgeting for interface timing is a topic too broad to resolve here. There are several resources on the web, including one done by TI for RGMII. www.ti.com/lit/an/snla243/snla243.pdf would be a good start.

    2) This would be a question for the Microchip team. From a Sitara MAC perspective, our boot ROM expects to see an industry standard PHY attached. There are no accommodations made for a switch so you would need to ensure that none are required for same.
  • 0 in reply to -DK-
    Expert 2765 points

    Hi DK,

    Thanks for the detailed answer again. I understand that for timing analysis I'll have to work that out, but I'm trying to get a sense of which parameter caught you eye when you mentioned extremely tight timing requirements. RMII is a standard interface for all manufacturers, so I'm just curious to know if there is any issue.

    Thank you for your help and patience :)

    Regards

    Santhosh

  • 0 in reply to Santhosh Ramani
    TI__Mastermind 27890 points
    Santhosh,
    True, RMII is an industry standard, but each device has it's own internal requirements for timing (setup/hold/delay). Each device on it's own may meet the interface requirements, but when combined to create a bus in a particular PCB design, they may not. This is why we require that customers perform a timing analysis of their particular design.

    As I recall, the PHY's output delay MIN/MAX are such that the Sitara MAC setup requirements are hard to meet in a typical topology.
  • 0 in reply to -DK-
    Expert 2765 points

    Hi DK,

    I'm attaching an analysis of the Microchip and TI PHYs along with AM335x and I'm unable to see significant difference between the 3 options. Can you please let me know if you are concerned about the 4ns and 2ns numbers?

    Thank you once again.

    Regards

    Santhosh

    RMII_Timing.pdf

  • 0 in reply to Santhosh Ramani
    TI__Mastermind 27890 points
    Santhosh,
    We do not provide analysis feedback beyond what our devices require. That information is presented in the relevant datasheet. I only commented on the other thread as it was device that I had not seen before and my curiosity was piqued.

    I will say that in this case the KSZ device output delay would be difficult to implement with the Sitara MAC. Note that the KSZ device has a 16ns maximum output delay which doesn't leave much margin for the attached MAC or (board propagation delays) when considering the RMII 20ns clock cycle.
  • 0 in reply to -DK-
    TI__Mastermind 22391 points

    Hi Santhosh

    let me answer the 2nd question with the Ethernet boot. Yes you can boot from the CPSW. i suggest you refer to the TRM section 

    26.1.9.4 EMAC Boot Procedure

    It has all the details you need. Let me know if this is what you are looking for.

    i will look into the PHY timing.

    Regards

    Mohsen

  • 0 in reply to Mohsen Khayami
    TI__Mastermind 22391 points
    Hi Santhos
    Just like to make sure so you are connecting the AM335x RMII MAC to the MAC of The switch? why not use the 2 port switch on the AM335? We usually connect the MAC to the phy but not to the switch.

    Regards
    Mohsen