SDRAM design rules for AM3505

In table 6-31, the maximum length mismatch between sdrc_ba[x], sdrc_ncs[x], sdrc_a[x], sdrc_ncas, sdrc_nras, sdrc_nwe, and sdrc_cke0 is shown as being 100 mils. In the same table, the nominal length of all those signals is shown as CACLM +/- 50 mils, where CACLM is the maximum Manhattan distance of any of those traces. Strictly speaking, however, the Manhattan distance of a trace that starts at (X1,Y1) and ends at (X2,Y2) is |X1-X2| + |Y1-Y2|.

Looking at the LogicPD Gerbers, though, it appears to me that those traces are longer than that Manhattan distance, and so my suspicion is that really, CACLM is the length of the longest trace of that group, and that, because the maximum trace length mismatch is 100 mils, the nominal trace length for that group (line 5 in table 6-31) should be called out as minimum CACLM-100, typical CACLM, max CACLM (since, if CACLM is the length of the longest trace, it is also by definition the maximum length).

I have a similar concern with the nominal trace lengths and acceptable trace length mismatch called out in table 6-32 for each of the DQx signal net classes as specified in table 6-29. In this case, DQLM is the variable that I believe should be defined as the longest trace of the group, and item 4 in table 6-32 should be defined as DQLM-100/DQLM/DQLM.

Am I correct in my interpretation, or am I not clearly visualizing the lengths of the traces on the LogicPD SoM?

Also, according to section 6.4.2.2, the PCB stackup must be a minimum of 6 layers, but according to the ZCN escape routing app note, a 4-layer board should be possible. Is the 6-layer requirement related to the fact that it's easier to put the power plane on the topmost inner layer, forcing the ground plane for impedance-matching of the differential pairs to be nearer the bottom of the PCB, or is there some other esoteric reason that the board must be 6 layers?