DSP goes to reset state

Can you make a straight up while(1) test and make it run reliably?  How about the same "while(1) test" running in DDR?  If that works then you can either start from your complete program and start stripping things out until it works, or you can start from your "while(1) test" and start adding stuff to it until it breaks.  That should help you to narrow your search.

This simple example works ok. But this project is rather complicated. In every core we have from 7 to 12 tasks. Every task communicates with FPGA board, and also works with DDR and send messages to each other (Really we have 2 DSP boards that also communicate with each other via SRIO). So this system can go to reset after 10 minutes or after 2 hours...so I can not begin with simple while(1) =)). Also the problem is that all caores are nearly "full". So I want to find what can cause reset. For example can it be that after memory corruption program counter jumps to 0x0000000 and that causes reset or smth. like that?

Well, the only thing supposed to reset the device is the watchdog interrupt.  If that's not the case then something "bad" is happening.  I've seen similar undefined behavior in the past as a result of accesses to reserved memory ranges.  You could potentially setup data watchpoints on reserved memory ranges to try and "catch" one of these accesses, if that is in fact the case...

PS.  There's also usual suspects like stack overflow, etc  See this page for more tips:

http://processors.wiki.ti.com/index.php?title=DSP_BIOS_Debugging_Tips

Thank you. I will try!