Compiler/AM3352: DDR3 timing issue

user4501000

Part Number: AM3352

Tool/software: TI C/C++ Compiler

Hi Sir

[Ti AM3352] DDR3-400 512MB tDQSS test fail

We have one issue, When we measure DRAM 512MB/400Mhz tDQSS item , We get the fail result , Could you help us to check this issue ? thanks.

Pls review the following link for more details.

Thanks

Shih-Chin

https://drive.google.com/open?id=10Tz5BlYohWVor2o9-Soqv0d5_dkqMcSG

over 7 years ago

0 JJD over 7 years ago

TI__Guru* 91890 points

Shih-Chin, did you perform the software leveling procedure found here?

processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

This will further optimize tDQSS and other parameters. If you have done this exercise and still see the issue, please attach Ratio Seed spreadsheet, and AC timing spreadsheet along with the DDR part number

Regards,
James

0 JJD over 7 years ago in reply to JJD

TI__Guru* 91890 points

One other question: what is the DDR topology in your design. Are you using T-topology or fly by.

Regards,
James

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Compiler/AM3352: DDR3 timing issue