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RTOS/DRA71: BIOS cfg file

Part Number: DRA71
Other Parts Discussed in Thread: SYSBIOS

Tool/software: TI-RTOS

Hi

We meet a probleam aboout the timer.

(1) In the Uboot , the timer 2 was used .

(2) In the DSP(C66) project , the timer 2 was configured in the C66.cfg.

Some times , the modules use the timer2 would be timeout , we doubt that it confilect with the timer 2  in the C66.cfg.

I hav teh questions :

(1)What the timer configure in c66. cfg ued for?

(2)As in our project ,we also develop ipu ,why there are no timers configure in IPU.cfg?

(3) I had try to change the timer id in the c66.cfg, errors would happen during building. (.Instance#1 : Timer device unavailable.)

(4) Do you have some materials about the SYS/BIOS cfg files?

cfg file:

var Task = xdc.useModule('ti.sysbios.knl.Task');
var Task        = xdc.useModule("ti.sysbios.knl.Task");
var Idle        = xdc.useModule("ti.sysbios.knl.Idle");
var BIOS        = xdc.useModule("ti.sysbios.BIOS");
var Startup     = xdc.useModule("xdc.runtime.Startup");
var SysStd      = xdc.useModule("xdc.runtime.SysStd");
var System      = xdc.useModule("xdc.runtime.System");
System.SupportProxy = SysStd;

var Log         = xdc.useModule("xdc.runtime.Log");
var Assert      = xdc.useModule("xdc.runtime.Assert");
var Program     = xdc.useModule("xdc.cfg.Program");
var Main        = xdc.useModule("xdc.runtime.Main");
var Memory      = xdc.useModule("xdc.runtime.Memory");
var Diags       = xdc.useModule("xdc.runtime.Diags");
var Semaphore   = xdc.useModule("ti.sysbios.knl.Semaphore");
var HeapMem     = xdc.useModule("ti.sysbios.heaps.HeapMem");
var HeapBuf     = xdc.useModule("ti.sysbios.heaps.HeapBuf");
var Clock       = xdc.useModule("ti.sysbios.knl.Clock");
var Timestamp   = xdc.useModule("xdc.runtime.Timestamp");
var Load        = xdc.useModule('ti.sysbios.utils.Load');
var Hwi         = xdc.useModule('ti.sysbios.hal.Hwi');
var Queue       = xdc.useModule('ti.sysbios.knl.Queue');
var SyncSem     = xdc.useModule('ti.sysbios.syncs.SyncSem');
var Cache       = xdc.useModule('ti.sysbios.hal.Cache');
var halCore     = xdc.useModule('ti.sysbios.hal.Core');
var GateH       = xdc.useModule('xdc.runtime.knl.GateH');
var Event       = xdc.useModule('ti.sysbios.knl.Event');
var biosGates   = xdc.useModule('ti.sysbios.gates.GateTask');

var BIOS = xdc.useModule('ti.sysbios.BIOS');
BIOS.cpuFreq.hi = 0;
BIOS.cpuFreq.lo = 500000000;

/***********************************************
 *          Reset Module Configuration         *
 ***********************************************/
//var Reset = xdc.useModule("xdc.runtime.Reset");
//Reset.fxns[Reset.fxns.length++] = "&Utils_dspMPUConfig";

var Hwi = xdc.useModule('ti.sysbios.hal.Hwi');
var ti_sysbios_family_c64p_Hwi = xdc.useModule('ti.sysbios.family.c64p.Hwi');
var Semaphore = xdc.useModule('ti.sysbios.knl.Semaphore');
var Startup = xdc.useModule('xdc.runtime.Startup');
var Timestamp = xdc.useModule('xdc.runtime.Timestamp');
var Memory = xdc.useModule('xdc.runtime.Memory');
var BiosCache = xdc.useModule('ti.sysbios.hal.Cache');
var ti_sysbios_family_c66_Cache = xdc.useModule('ti.sysbios.family.c66.Cache');
var HeapMem = xdc.useModule('ti.sysbios.heaps.HeapMem');
var HeapBuf = xdc.useModule('ti.sysbios.heaps.HeapBuf');
//var CpIntc = xdc.useModule('ti.sysbios.family.c66.tci66xx.CpIntc');
var EventCombiner = xdc.useModule('ti.sysbios.family.c64p.EventCombiner');
var Exception = xdc.useModule('ti.sysbios.family.c64p.Exception');
var System = xdc.useModule('xdc.runtime.System');
var Cache     = xdc.useModule('ti.sysbios.family.c66.Cache');
var Idle = xdc.useModule('ti.sysbios.knl.Idle');
var Load = xdc.useModule('ti.sysbios.utils.Load');

//Program.sectMap[".vecs"] = "L2SRAM_CODE";

//Task.defaultStackSize = 0x40000;
//Program.stack = 0x40000;
BIOS.heapSize = 0x100000;
//Program.heap = 0x40000;
//BIOS.libType = BIOS.LibType_Instrumented;

/* BIOS library type, same setting is used by IPC as well */
//BIOS.libType = BIOS.LibType_Custom;
BIOS.libType = BIOS.LibType_Debug;
//BIOS.libType = BIOS.LibType_Instrumented;

/* load calculation related settings */
if(BIOS.libType==BIOS.LibType_NonInstrumented)
{
    /* cannot enable these load measurement in non-instrumented libraries */
    Load.swiEnabled   = false;
    Load.hwiEnabled   = false;
    Load.taskEnabled  = false;
}
else
{
    Load.swiEnabled   = true;
    Load.hwiEnabled   = true;
    Load.taskEnabled  = true;

}

Clock.tickMode = Clock.TickMode_PERIODIC;
Clock.tickSource = Clock.TickSource_USER;


var TimerSupport = xdc.useModule('ti.sysbios.family.shared.vayu.TimerSupport');
TimerSupport.availMask = 0x0003;

/***********************************************
*           Timer Module Configuraion         *
***********************************************/
var Timer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');

Timer.intFreq.hi = 0;
/* system clock runs at 20 MHz */
Timer.intFreq.lo = 20000000;
Timer.checkFrequency = false;

var timerParams = new Timer.Params();
timerParams.period = 1000;
timerParams.twer.ovf_wup_ena = 1;
timerParams.tiocpCfg.emufree = 1;
timerParams.tsicr.posted = 0;
Timer.create(0, '&mainDsp1TimerTick', timerParams);

var DMTimer = xdc.useModule('ti.sysbios.timers.dmtimer.Timer');
DMTimer.checkFrequency = false;
var timerParams2 = new DMTimer.Params();
timerParams2.tsicr.posted = 0;
DMTimer.intFreq.hi = 0;
DMTimer.intFreq.lo = 20000000;
var DMTimestampProvider = xdc.useModule("ti.sysbios.timers.dmtimer.TimestampProvider");
DMTimestampProvider.timerId = 1;
DMTimestampProvider.useClockTimer = false;
var Timestamp = xdc.useModule("xdc.runtime.Timestamp");
Timestamp.SupportProxy = DMTimestampProvider;

  • Hi,

    user5183370 said:
    (1)What the timer configure in c66. cfg ued for?

    SYS/BIOS uses the Timer module to drive the OS system tick. System tick is the fundamental time unit used by RTOS which provides the infrastructure for the scheduler to unblock tasks to run at specific times. Any system API which uses a timeout will refer to the timeout in terms of ticks. E.g. Task_sleep(10) will sleep for 10 ticks. Tick time is configurable but by default is 1ms. The timer is used for SYS/BIOS running on all CPUs (C66x, IPU, A15) in a similar way.

    user5183370 said:
    (2)As in our project ,we also develop ipu ,why there are no timers configure in IPU.cfg?

    IPU is also using a system timer. Even though it may not be in the .cfg file explicitly, it is a dependent module needed by BIOS scheduler and will get included under the hood anyway when you run the configuration process. See software-dl.ti.com/.../TimerSupport.html for the default list of timers used for each instance of each CPU.

    user5183370 said:
    (3) I had try to change the timer id in the c66.cfg, errors would happen during building. (.Instance#1 : Timer device unavailable.)

    Ideally, you don't need to modify the default timer IDs for your OS timer tick unless you have a specific reason you need to shuffle the resources. Are you trying to use timers for something else in your application? Also, where did you get this sample .cfg file from?

    user5183370 said:
    (4) Do you have some materials about the SYS/BIOS cfg files?

    I would recommend you review the Bios_User_Guide.pdf which is included in the docs folder of your SYS/BIOS installation. Chapter 2.3 discusses configuration files and Chapter 5 reviews timing services.

    Thanks,

    Stephen

  • Hi

    (2)As in our project ,we also develop ipu ,why there are no timers configure in IPU.cfg?

     

  • user5183370 said:
    CPU will use the deafult timer mapping for sys/bios, even developers did not configure timers in cfg files?

    Yes, that's correct.  The configuration file will pull in the default and configure for the user even if not explicitly setup in the script.  The comments in the table are correct, so depending on which IPU instance and core number, you will by default be using either GP Timer 3, 4, 9, or 11.

    Thanks,

    Stephen

  • Hi

    As the table shouwn:

     | A15          | 0x0202 (GPTimer 2 & 10)     |
      | DSP          | 0x0030 (GPTimer 5 & 6)      |
      | IPU(Dual-M4) | 0x050C (GPTimer 3,4,9 & 11) |
      | ARP32        | 0x00C0 (GPTimer 7 & 8)      |
       --------------------------------------------

    Each M4 core need a timer for its SYS/BIOS,right?

    1. Now,in our project.DSP use the default GPTimer 5 for SYS/BIOS ,and it was congured in cfg files.

        And in IPU cfg files ,there are not explicitly setup in the script.

     In this condition, the DSP woks well, but some modules in IPU , such as I2C ,woks bad , timer out errors happen in I2C modules.

    2. DSP use the default GPTimer 5 for SYS/BIOS ,and it was congured in cfg files.

        IPU use the GPTimer 11 for SYS/BIOS ,and it was congured in cfg files.

        In this condition,ipu & dsp both works well.

    3.As I develop 2 M4 Cores,  how can I know that what i used is IPU 0 M4 CORE0 & M4 CORE1  or  IPU 1 M4 CORE0 & M4 CORE1 or IPU 0 M4 CORE0 &IPU 1 M4 CORE0 or  ......

    4.As I develop 2 M4 Cores,  I tried to configure two different GPTimers in each cfg file,but in my test result ,when GPTimer 3,4,9  configured for each M4 core, m4 cores could not boot up.

      Only

  • Hi

    Sorry for last email.

    As the table shouwn:

    | A15 | 0x0202 (GPTimer 2 & 10) |
    | DSP | 0x0030 (GPTimer 5 & 6) |
    | IPU(Dual-M4) | 0x050C (GPTimer 3,4,9 & 11) |
    | ARP32 | 0x00C0 (GPTimer 7 & 8) |
    --------------------------------------------

    Each M4 core need a timer for its SYS/BIOS,right?

    1. Now,in our project.DSP use the default GPTimer 5 for SYS/BIOS ,and it was congured in cfg files.

    And in IPU cfg files ,there are not explicitly setup in the script.

    In this condition, the DSP woks well, but some modules in IPU , such as I2C ,woks bad , timer out errors happen in I2C modules.

    2. DSP use the default GPTimer 5 for SYS/BIOS ,and it was congured in cfg files.

    IPU use the GPTimer 11 for SYS/BIOS ,and it was congured in cfg files.

    In this condition,ipu & dsp both works well.

    3.As I develop 2 M4 Cores, how can I know that what i used is IPU 0 M4 CORE0 & M4 CORE1 or IPU 1 M4 CORE0 & M4 CORE1 or IPU 0 M4 CORE0 &IPU 1 M4 CORE0 or ......

    4.As I develop 2 M4 Cores, I tried to configure two different GPTimers in each cfg file,but in my test result ,when GPTimer 3,4,9 configured for each M4 core, m4 cores could not boot up.

    4.As I develop 2 M4 Cores, I tried to configure two different GPTimers in each cfg file,but in my test result ,when GPTimer 3,4,9 configured for each M4 core, m4 cores could not boot up. pls help check about teh reasons for this probleam.

    Thanks.
  • Hi,

    user5183370 said:
    Each M4 core need a timer for its SYS/BIOS,right?

    This is mostly true.  The only exception is if you are configuring the cluster to run SMP BIOS, which in that case one system tick will drive synchronous operation of both cores.  Otherwise, if you are running independent BIOS images on each CPU, then yes, separate timers are needed for each core.

    user5183370 said:
    In this condition, the DSP woks well, but some modules in IPU , such as I2C ,woks bad , timer out errors happen in I2C modules.

    There are many things which can cause this.  Which IPU instance/core do you see this issue?  Is it possible that interrupt numbers are conflicting between I2C and the timer?  GPTimer 3, 4, 9, and 11 uses HWI numbers 53, 54, 55, and 56 by default, respectively.  What is the I2C interrupt number used?

    user5183370 said:
    3.As I develop 2 M4 Cores, how can I know that what i used is IPU 0 M4 CORE0 & M4 CORE1 or IPU 1 M4 CORE0 & M4 CORE1 or IPU 0 M4 CORE0 &IPU 1 M4 CORE0 or ......

    This must be comprehended by the build system.  Your CCS project or makefile needs to know which IPU instance and core number is being configured.  There is a ti.sysbios.family.arm.ducati.Core module which allows you to specify the(core)  id and ipuId which may be needed for other modules (e.g. ti.sysbios.family.shared.vayu.IntXbar).  There is hardware capability to detect core instance but not IPU instance.

    user5183370 said:
    4.As I develop 2 M4 Cores, I tried to configure two different GPTimers in each cfg file,but in my test result ,when GPTimer 3,4,9 configured for each M4 core, m4 cores could not boot up.

    You can reconfigure system tick source in many ways.  Simplest way would be to use the TimerSupport module and limit the availability mask for each IPU instance/core you are building.  Or, you could leave the mask as-is but then override the timer used for the tick function in the configuration - see an example in the SYS/BIOS API doc: 

    Thanks,

    Stephen

  • Hi Stephen

    Thanks you for your patience explaination.

    I make a further understanding of SYS/BIOS.

    Now, I still have some probleams, pls help take a analysis.

    1. I review the code in SBL, I found that there are timer's enbale operations .So I tried to enbale timer 3/4/9/11 in turn ,and i changed the timer id to 3/4/9/11 in ipu.cfg. Then IPU could boot up.

    So, I doubt that , if the ipu want to use a timer to work as a tick for SYS/BIOS, the timer should be enabled in SBL first,right ?

    2. As I didn't enable the SMP SYS/BIOS. cloud i use the same timer for two M4 cores? (In my test ,i used the same timer ,it seems that it works well).

    3. According the phenomenon of 1. I review the timer configuration for timer5/6. Strangely , timer5& timer6 were not enabled in SBL, but the dsp core could boot up. if 1 is right ,I couldn't explain 3 .pls help take a look.

    Thanks.

  • Hi,

    user5183370 said:
    So, I doubt that , if the ipu want to use a timer to work as a tick for SYS/BIOS, the timer should be enabled in SBL first,right ?

    Which SDK are you using?  I also am wondering what was the starting point for the .cfg files you are using?  I'm not 100% sure how the SBL configuration is affecting your operation.  There could be some larger system level issues creating conflicts (e.g. AMMU).

    user5183370 said:
    2. As I didn't enable the SMP SYS/BIOS. cloud i use the same timer for two M4 cores? (In my test ,i used the same timer ,it seems that it works well).

    Yes, for SMP, a single system tick is used.  This is because only a single BIOS instance (and hence, a single scheduler) runs across the two cores.

    user5183370 said:
    3. According the phenomenon of 1. I review the timer configuration for timer5/6. Strangely , timer5& timer6 were not enabled in SBL, but the dsp core could boot up. if 1 is right ,I couldn't explain 3 .pls help take a look.

    In general, and by default, the application images for each core will configure its own respective timer as part of the BIOS startup sequence.  There are exceptions here depending on how customized this configuration is in the application.

    Thanks,

    Stephen