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EVM6472 emac1 don't work

Ruben Liber
Prodigy 40 points

We buy 4 evm6472 for development. We are working with DUAL_EMAC  example that comes with the CSL. With the network analyzer WIRESHARK only see packets transmitted by emac0. The emac1 not transmit and not receive packets. Any help will be appreciated.

  • 0
    TI__Intellectual 910 points

    Please make sure that the

    GPIO5_EMAC1_EN pin is pulled correctly. It should be high.

    regards,

    yanmin

  • 0 in reply to nmin Wu
    Prodigy 40 points

    Thank you very much for responding so quickly.
    Table 3-1 (Fixed Configuration) TMDSEVM6472_UserGuide.pdf file specifies that the EMAC1_EN(GP05) is "1" by default.
    If I never changed, could be in the low state "0"?. How I can check?. If the current is low "0", how I can change?, Since the GP05 pin is connected to the FPGA.
    Moreover, your suggestion would seem appropriate because the emac1 never "UP" the physical link.

    regards

    Ruben

  • 0 in reply to Ruben Liber
    TI__Intellectual 910 points

    You can check the DEVCTL register to see the status of EMAC1.

  • 0 in reply to nmin Wu
    Prodigy 40 points

    nmin thank you very much again for your response. I checked  the DEVSTATE in the menu of CCSv4 Scripts-> Device Configuration-> check_DEVSTAT and then detailed the results shown in the console output:

    DEVSTAT = 0x00818363
      DDR2 Mem Controller pins = enable.
      CFGP[2:0] = 0.
      SYSCLKOUTEN pin = SYSCLK4 mode.
      UTOPIA/EMAC pins = EMAC pins enable.
      RGMII Interface Selected.
      RGMII Interface Selected.
      Endianness = little endian.
      Bootmode = Master I2C boot for 51

    Here also detailed the general configuration of EVM6472. In the menu of CCSv4 Scripts-> Device Configuration-> check_device_configuration and then detailed the results shown in the console output:

    PLL1 Controller Configuration
      PLL1 Controller is in PLL mode.
      PLL multiply value = 25.
      CPU frequency = 625.0 MHz.
      PLLDIV10 =
    enable
    divide by 3,
    SYSCLK10 frecuency = 208.3333 MHz.
    PLL2 Controller Configuration
      PLLDIV1 =
    enable,
    divide by 2,
    SYSCLK1 frequency = 250.0 MHz.
    DEVSTAT = 0x00818363
      DDR2 Mem Controller pins = enable.
      CFGP[2:0] = 0.
      SYSCLKOUTEN pin = SYSCLK4 mode.
      UTOPIA/EMAC pins = EMAC pins enable.
      RGMII Interface Selected.
      RGMII Interface Selected.
      Endianness = little endian.
      Bootmode = Master I2C boot for 51

    I hope that this information would be useful to be able to help me.

    Regards.

    Ruben

     

  • 0 in reply to Ruben Liber
    Prodigy 40 points

    I look DEVCTL = 0x000011F9,  EMAC1 is enable

    Regards

    Ricardo