Hi all
I'm using a DM365 (not an EVM board) and have a requirement to use a 'non-standard' video output mode - that is, with VENC_VMOD.VMD = 1. If I understand correctly, setting this to 1 allows me to use the various VENC timing registers to set the position and width etc. of the Horizontal and vertical sync signals. I presume one way of looking at the 'standard' modes' (set by eg. VENC_VMOD.TVTYP) is that they are equivalent to 'preset' collections of these HSync and VSync register settings?
Anyway ... having set VENC.VMOD = 1, I have been trying without success to get even a 'standard' resolution out. One problem is that the descriptions of the various registers are not very clear. I'm looking at the VPBE User guide SPRUFG9B.pdf. Figure 39 on pp. 72 shows an example display fram and control signal definitions. However it's not very clear, and also doesn;t show the effect of the Horizontal and Vertical Sync Delay registers, VENC_HSDLY and VENC_VSDLY.
The description of register HSDLY (SPRUFG9B pp 251) says "Output delay of horizontal sync signal. This can delay horizontal sync output from HSYNC pin by 1FFFh ENC clock." But it doesn't say what this is relative to.The beginning of a line? The end of valid data? or what?
So my initial questions on this are: Can you explain how (eg) HSDLY, HVALID, HINT, HSPLS, HINTVL combine to produce the more commonly quoted Front Porch and back porch times?
And also: have you, for example, a set of values for (HSPLS, VSPLS, HINTVL, HSTART, HVALID, VINT, VSTART, VVALID, HSDLY, VSDLY) that correspond to one of the 'standard' modes, that I could use as a basis for some further experimenting?
Thanks very much.
Regards
Jon Nicoll