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Original question:

CCS / 66AK2L06：66AK2L06 EVM DFE IN BYPASS MODE

编译/ 66AK2L06： CCS / 66AK2L06：66AK2L06 EVM DFE IN BYPASS MODE

CHEN
Prodigy 160 points
Part Number: 66AK2L06
Other Parts Discussed in Thread: RFSDK, DAC38J84, ADC14X250

Tool/software: TI C/C++ Compiler

,how is DFE in " DFE BYPASS MODE"? Is there a DFE BYPASS example? 

  • 0
    TI__Mastermind 37500 points
    The 66aK2L06 - DFE bypass mode, is a signal processing bypass, not a block bypass.
    - DFE bypass means that the TxBB IQ rate, and Tx stream IQ rate are the same.
    - DFE bypass means that the Rx BB IQ rate and Rx stream IQ rate are the same.

    The closest TIDEP, is the 66aK2l06 & 14x250 - demo2 245.76Msps real ADC input, 122.88Mhz IQ complex output.
    The Rx real to complex, and PFIR - Rx filter are the only signal processing performed on the receive path. The transmit path
    in this example has a Tx-PFIR filter, 3/2 interpolating resampler, and 3/2 decimating resampler, to achieve an 122.88Mhz complex output.

    Suggest using the demo2, first then customizing.

    The DFE bypass possible combinations are:
    num BB signals Tx/Rx, BBTx/Rx IQ rate, num Tx/Rx streams, Tx/Rx stream IQ rate, format, num JESD lanes, LMF, DFE clock, notes
    1, 122.88e6, 1, 122.88e6, interleaved IQ, 1, 124, 368.64, Tx is not DFE bypass- due to Resampler, Rx is signal processing bypass
    1, 122.88e6, 1, 245.76e6, parallel IQ, 2, 222, 368.64, Tx is not DFE bypass-due to Resampler, Rx takes I or Q real, has R2C, the rest of Rx is bypass

    2, 92.16e6, 2, 92.16e6, interleaved IQ, 2, 244, 368.64, Tx and Rx are signal processing bypass
    2, 61.44e6, 2, 61.44e6, interleaved IQ, 2, 244, 245.76, Tx and Rx are signal processing bypass
    4, 46.08e6, 4, 46.08e6, TDM interleaved IQ, 2, 288, 368.64, Tx and Rx are signal processing bypass
    4, 30.72e6, 4, 30.72e6, TDM interleaved IQ, 2, 288, 245.76, Tx and Rx are signal processing bypass

    Regards,
    Joe Quintal
  • 0 in reply to Radio-Joe
    Prodigy 160 points
    hello；
    TI \ pdk_keystone2_3_01_03_06\packages\exampleProjects\dfeUnitK2LTestProject.
    this is file useful?
    Bypass mode by modifying this file?
  • 0 in reply to CHEN
    TI__Mastermind 37500 points

    Hello

    There is an infrastructure for controlling the internal DMA structure from DDR3 memory to IQNet buffers to DFE, to JESD, to Serdes and the Rx is the reverse order.

    The infrastructure is called RFSDK, " http://www.ti.com/tool/rfsdk    "

    Within the RFSDK concept there is a 66AK2L06, ADC14x250, DAC38J84, and DLC card that are part of a TI design.   " tidub89 "

    This is the closest released configuration to DFE bypass

    Tx is not DFE bypassed

    input 122.88e6 -> DDUCTx PFIR filter, Resampler 3/2 184.32, CFR is effectively bypassed, CDFR Resample 4/3, DPD and Tx Frequency translates to 61.44 transmitted at 245.76Msps Tx, 

    on the Rx side 245.76Msps real, 

    Lane0 takes the I data from DAC IQ,the Rx performs Hilbert transform 61.44 -> 0, 122.88Msps complex, the Rx passes the 122.88msps to the Rx DDUC.

    The Rx DDUC PFIR filters.

    Please setup to use this configuration.

    Regards,

    Joe Quintal