I am trying to interface a 320x240 RBG666 LCD to the DM355. I think I have a handle on the interaction between uboot params, davinci_platform.c and logicpd_encoder.c and the header files related to the various modes. I have modified the 640x400 mode initially to develop my interface to try and hold some of the world still.
However I have problems understanding the process to change the pixel clock on the VPBE output port to a range that my LCD can work with (say 6-10MHz) I think that I should be able to modify this pixel clock using SYSCLK3 via PLLDIV3 however others have reported this will provide a lowest clock of 13.5MHz without reducing the main DM355 core. Can anybody help with this issue? Documentation that explains the process would be ideal but I cannot seem to locate this.
Related to the same point, is there any reason why MX2 clock could not be either used with a different frequency (accepted that the internal encoder will not work but I don’t need it) crystal or clock to provide either a lower frequency for the LCD (switched to become the clock source via the clock control registers) or a higher frequency for HD apps?
Any help welcomed.
