Compiler/EVMK2H: Getting other timers besides timer 0 working with CSL

Alfredo Sepulveda

Part Number: EVMK2H

Tool/software: TI C/C++ Compiler

Hey all,

I'm working with the DSP's i have successfully used the CSL, and only the CSL, to use timer0 to generate interrupts but when i tried the same approach with timer 1 I was unsuccessful. Also when I created the timer I had to use the local events for the timer, instead of the CIC event numbers. I thought that you had to first enable the CIC modules to activate the interrupts. This was not the case. the event was subscribed to vector 12. I don't know what changes would have to be added to get timer 1 working alongside timer0.

How does the CSL play with the CIC, It was my suspicion that your libs worked in the background to configure these chip interrupts, but in this case the values were not used. does this mean that the timer API's were made as primary events not secondary?

I followed the example code under ti/csl/example/timer/timer_test.c

I found values that worked with the K2H but only for timer0. Is this by design or is there a way to use any other timer?

Changes I made:

CSL_GEM_TINTHN = 65

CSL_GEM_TINTHL = 64

IntcInstance = 1

// The libraries didn't define these but i figured this was right

CSL_TMR_0 = 0

I added the GPIO/ TIMER / UART /CSL libraries just in case I needed them

also the watchdog functionality did not work as is presented in the example code

over 6 years ago

0 lding over 6 years ago

TI__Guru* 95265 points

Hi,

I think you looked at pdk_k2hk_4_0_x\packages\ti\csl\example\timer for the test. The test code used: CSL_TMR_0 in the test. I searched the CSL folder, and saw CSL_TMR_x are only defined for Keystone I device (C6657 and C6678), so I am not sure if this timer example is ever tested on K2H.

Regards, Eric

0 lding over 6 years ago in reply to lding

TI__Guru* 95265 points

Hi,

You may look at this: processors.wiki.ti.com/.../Configuring_Interrupts_on_Keystone_Devices

From the K2H datasheet:
Table 8-24. CIC0 Event Inputs — C66x CorePac Secondary Interrupts (continued)
175 TIMER_7_INTL Timer interrupt low(1)
176 TIMER_7_INTH Timer interrupt high(1)
177 TIMER_6_INTL Timer interrupt low(1)
178 TIMER_6_INTH Timer interrupt high(1)
179 TIMER_5_INTL Timer interrupt low(1)
180 TIMER_5_INTH Timer interrupt high(1)
181 TIMER_4_INTL Timer interrupt low(1)
182 TIMER_4_INTH Timer interrupt high(1)
183 TIMER_3_INTL Timer interrupt low
184 TIMER_3_INTH Timer interrupt high
185 TIMER_2_INTL Timer interrupt low
186 TIMER_2_INTH Timer interrupt high
187 TIMER_1_INTL Timer interrupt low
188 TIMER_1_INTH Timer interrupt high
189 TIMER_0_INTL Timer interrupt low
190 TIMER_0_INTH Timer interrupt high

Those are secondary interrupts. If you follow above link to configure both INTC and CIC, it should work for Timer 0 and Timer 1.

Regards, Eric

0 Alfredo Sepulveda over 6 years ago in reply to lding

Intellectual 790 points

So how does this mesh with the TmrLibarary? All this does is map the interrupt events to the vectors. I attempted to link the timer intcobj with the CIC module as shown in the example but nothing happened.

Questions:
There's this in the section you linked
/* Map System Interrupt to Channel. */
/* Note that hyplnk_EXAMPLE_INTC_OUTPUT = 32 + (11 * CoreNumber) = 43 for Core0*/
CSL_CPINTC_mapSystemIntrToChannel (hnd, CSL_INTC0_VUSR_INT_O, hyplnk_EXAMPLE_INTC_OUTPUT);

There is a calculation here between the interrupt number for the going from the CIC to the INTC, I can't seem to figure out where these numbers come from.
What is the relation between the event number and the interrupt number going from the CIC into the INTC module on this platform all i could find were the vent numbers not the interrupt numbers

what does the output 43 have to do with the event id presented in the example?

0 lding over 6 years ago in reply to Alfredo Sepulveda

TI__Guru* 95265 points

Hi,

The example you referred to is for C6678 Hyperlink interrupt, the concept is similar to K2H: the interrupt number may be different but they all secondary.

You can refer to pdk_k2hk_4_0_x\packages\ti\drv\hyplnk\example\common\hyplnkIsr.c,

void hyplnkExampleInstallIsr (void)
{
/* Setup up the core-specific INTC */
if (hyplnkExampleInitCoreIntc()) {
printf ("Failed to set up CorePac INTC\n");
exit(1);
}

/* Connect hyperlink's common interrupt to a CorePac event */
if (hyplnkExampleInitChipIntc()) {
printf ("Failed to set up Chip INTC\n");
exit(1);
}

/* Connect the CorePac event to a vector */
if (hyplnkExampleInitVec()) {
printf ("Failed to set up interrupt vector\n");
exit(1);
}
}

This is the same function for C6678 and K2H, and you can replace it with your Timer 0.

1. Inside hyplnkExampleInitChipIntc(), the input is system interrupt, output is host interrupt:
system interrupt for C6678: 111 VUSR_INT_O HyperLink interrupt
system interrupt for K2H is: 111 HYPERLINK_0_INT HyperLink 0 interrupt
System interrupt for K2H (Your time case):
187 TIMER_1_INTL Timer interrupt low
188 TIMER_1_INTH Timer interrupt high
189 TIMER_0_INTL Timer interrupt low
190 TIMER_0_INTH Timer interrupt high

output is:
host interrupt for C6678: #define hyplnk_EXAMPLE_INTC_OUTPUT (32 + 11 * DNUM)
host interrupt for K2H: #define hyplnk_EXAMPLE_INTC_OUTPUT (64 + 10 * DNUM)===========> You can use this for Hyperlink or Timer

2. Inside hyplnkExampleInitVec(), the input is event ID (the same as host interrupt from above part 1), the output is CPU-interrupt-vector
event ID FOR c6678: 21 CIC0_OUT(32+0+11*n) (7) Or CIC1_OUT(32+0+11*(n-4)) (7) Interrupt Controller output======>this is in C6678 datasheet Figure 7-32 TMS320C6678 System Event Inputs — C66x CorePac Primary Interrupts (Sheet 1 of 4)

event ID for K2H: 45 CIC_OUT64_PLUS_10_MUL_N(2) CIC Interrupt Controller output(1) ======> this is in the 66AK2H14 datasheet Table 8-22. System Event Mapping — C66x CorePac Primary Interrupts (continued)

CPU-interrupt-vector: this is from 4 to 15.

Basically, in the above hyplnkExampleInstallIsr() example, you change the "111" to "187 or 188 or 189 or 190 ...." for different timers and keep the rest code the same, it should work.

Hope this is clear.

Regards, Eric

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Compiler/EVMK2H: Getting other timers besides timer 0 working with CSL