TDA2Px M4 IPU AMMU Questions

Andreas Vogt57

Hi,

I have some questions about the AMMU. I using for an working system the following configuration of the AMMU. I am not sure why I need some of the configurations, it would be nice if someone could help me!

For accessing the hardware I need to configure a large page witth mapping address 0x40000000 to 0x40000000? Is this correct? What happen if I want to access the IPU_BITBAND_REGION2 which is at address 0x40000000?
At reset, the MMU is loaded with page 0, which forces the L2 RAM to be address 0x0. Does this means that IPU_BOOT_SPACE does not exist any more and instead of IPU_BOOT_SPACE I have the IPU_RAM with the length of 64KB?
WUGEN_IPU registers have the virtual address 0x40000000. For that I need to configure a small page 0x55080000 to 0x40000000, right? Does the small page configuration collide or interact with the large page configuration (0x40000000 to 0x40000000)?

 ammuPageConfig_t pageConfig = {0U};

   // LARGE -------------------------------------------------------
   // Mapping L4_CFG
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_LARGE;
   pageConfig.ammuPageNum     = 0U;
   pageConfig.policyRegVal    = 0x00000003; // (512MB | ENABLE)
   pageConfig.physicalAddress = 0x40000000;
   pageConfig.logicalAddress  = 0x40000000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // Mapping Firmware
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_LARGE;
   pageConfig.ammuPageNum     = 1U;
   pageConfig.policyRegVal    = 0x000B0003; // (WRITE_BACK | POSTED | L1_CACHABLE | 512MB | ENABLE)
   pageConfig.physicalAddress = 0x9E000000;
   pageConfig.logicalAddress  = 0x9E000000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // MEDIUM ------------------------------------------------------
   // Mapping 1st EDMA
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_MEDIUM;
   pageConfig.ammuPageNum     = 0U;
   pageConfig.policyRegVal    = 0x00000003;
   pageConfig.physicalAddress = 0x43300000U;
   pageConfig.logicalAddress  = 0x63300000U;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // Mapping 2nd EDMA
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_MEDIUM;
   pageConfig.ammuPageNum     = 1U;
   pageConfig.policyRegVal    = 0x00000003;
   pageConfig.physicalAddress = 0x43400000U;
   pageConfig.logicalAddress  = 0x63400000U;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // SMALL --------------------------------------------------------
   // Mapping IPU_RAM: 1st 16KB
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_SMALL;
   pageConfig.ammuPageNum     = 0U;
   pageConfig.policyRegVal    = 0x0001000B; // (L1_CACHABLE | VOLATILE | 16KB |  ENABLE)
   pageConfig.physicalAddress = 0x55020000;
   pageConfig.logicalAddress  = 0x00000000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // IPU_UNICACHE_MMU, IPU_WUGEN and IPU_MMU are placed by remoteproc at the virtual address 0x40000000
   // P.A. 0x55080000U V.A. 0x40000000U
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_SMALL;
   pageConfig.ammuPageNum     = 1U;
   pageConfig.policyRegVal    = 0x0000000B; // (VOLATILE | 16KB |  ENABLE)
   pageConfig.physicalAddress = 0x55080000;
   pageConfig.logicalAddress  = 0x40000000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // Mapping IPU_RAM: 2nd 16KB
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_SMALL;
   pageConfig.ammuPageNum     = 2U;
   pageConfig.policyRegVal    = 0x0001000B; // (L1_CACHABLE | VOLATILE | 16KB |  ENABLE)
   pageConfig.physicalAddress = 0x55024000;
   pageConfig.logicalAddress  = 0x00004000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

   // Mapping IPU_RAM: 3nd 16KB
   pageConfig.ammuPageType    = AMMU_PAGE_TYPE_SMALL;
   pageConfig.ammuPageNum     = 3U;
   pageConfig.policyRegVal    = 0x0001000B; // (L1_CACHABLE | VOLATILE | 16KB |  ENABLE)
   pageConfig.physicalAddress = 0x55028000;
   pageConfig.logicalAddress  = 0x00008000;
   AMMUConfigPage(SOC_IPU1_UNICACHE_MMU_BASE, &pageConfig);

Thanks

over 6 years ago

0 Rishabh Garg over 6 years ago

TI__Guru 55685 points

Hi Andreas,

1. You cannot access bit band region. In case you want to access this space you need to map another large page/multiple small or medium pages depending upon your use cases and then access via this mapping. Usually a large page is used to map 0x6000_0000 virtual address to 0x4000_0000 physical address.
2. You can also decide to map only first 16 KB and put the boot code there.
3. In case of multiple mappings small page mapping takes precedence over medium which takes precedence over large.

Regards,
Rishabh

0 Andreas Vogt57 over 6 years ago in reply to Rishabh Garg

Intellectual 730 points

Hi Rishabh,

thanks for your answers.

Regarding 2:
I am still confused. "MMU is loaded with page 0, which forces the L2 RAM to be address 0x0" has nothing to do with my AMMU configuration, its the MMU right? Do I have to map 0x5502_0000 to 0x0000_0000 with the AMMU or can I just access the IPU_BOOT_SPACE. If 0x0 is always mapped to 0x5502_0000 by MMU, then I lose 16KB of IPU_BOOT_SPACE memory?

Regards,
Andreas

0 Rishabh Garg over 6 years ago in reply to Andreas Vogt57

TI__Guru 55685 points

Hi Andreas,

Have you gone through "IPU Boot Configuration" section of the TRM?

Regards,
Rishabh

0 Andreas Vogt57 over 6 years ago in reply to Rishabh Garg

Intellectual 730 points

Hi,

I have no such a section in my TRM (May 2017–Revised November 2017) or I can't find it.

Where I can find it? Can you give me a link?

Andreas

0 Rishabh Garg over 6 years ago in reply to Andreas Vogt57

TI__Guru 55685 points

Hi Andreas,

Can you specify the name of the document you are looking at.

Regards,
Rishabh

0 Andreas Vogt57 over 6 years ago in reply to Rishabh Garg

Intellectual 730 points

Hi,

TDA2Px
SoC for Advanced Driver Assistance
Systems (ADAS)
Silicon Revision 1.0
Texas Instruments ADAS Family of Products
Technical Reference Manual
Literature Number: SPRUIF0A
May 2017–Revised November 2017

Regards,
Andreas

0 Rishabh Garg over 6 years ago in reply to Andreas Vogt57

TI__Guru 55685 points

Hi Andreas,

It seems that this section is missing from this particular TRM. Please see below for contents of this section:

The IPU boot location is controlled via two Control Module registers:
• CTRL_CORE_CORTEX_M4_MMUADDRTRANSLTR[19:0] CORTEX_M4_MMUADDRTRANSLTR:
Used to set the physical translated address for IPU AMMU
• CTRL_CORE_CORTEX_M4_MMUADDRLOGICTR[19:0] CORTEX_M4_MMUADDRLOGICTR: Used
to set the logical source address for IPU AMMU
By default, two AMMU pages are enabled:
• Small page-0: Translates the 16KB address range from CORTEX_M4_MMUADDRLOGICTR to
(CORTEX_M4_MMUADDRLOGICTR + 0x3FFF). If CORTEX_M4_MMUADDRLOGICTR is set to
0x00000, page-0 will control the boot location. If the boot location needs to be mapped to the L2 RAM
(0x5502_0000), then CORTEX_M4_MMUADDRTRANSLTR needs to be set to 0x55020. This page is
set as non-cacheable at reset.
• Small page-1: Loaded with the physical address of the IPU AMMU configuration registers
(0x5508_0000 - 0x5508_0FFF), which is mapped to the virtual address range from 0x4000_0000 to
0x4000_0FFF. This page is also set as non-cacheable at reset.
NOTE: Small page-1 is by default 4KB. Software has to modify it to 16KB to cover L2MMU/WUGEN
masks.
For IPU to boot from any location in L3:
1. Provide boot address through CORTEX_M4_MMUADDRTRANSLTR to AMMU page-0
(CORTEX_M4_MMUADDRLOGICTR set to 0x00000). Keep L2 MMU disabled (or enable L2 MMU but
keep the same translation for 0x0; otherwise there will be L2-MMU page-walks / page-faults).
2. Set CORTEX_M4_MMUADDRTRANSLTR to 0x00000 (or any value). Host CPU re-programs AMMU
page to map 0x0 virtual address to a physical L2 RAM / L3 location. Only after the programming is
complete, Cortex-M4 reset is released. L2 MMU as described above.
3. Set CORTEX_M4_MMUADDRTRANSLTR to 0x00000 (no translation). Host CPU programs L2 MMU
to do the address translation for 0x0.
For IPU to boot from L2 RAM:
1. This must be done through AMMU page-0. Use either (1) or (2) as described above.

Regards,

Rishabh

0 Andreas Vogt57 over 6 years ago in reply to Rishabh Garg

Intellectual 730 points

Hi Rishabh,

i don't think that this section is missing, I think I have another document. Maybe other sections are also not included, so please send me a link to the newest TRM of TDA2px.

Andreas

0 Rishabh Garg over 6 years ago in reply to Andreas Vogt57

TI__Guru 55685 points

Hi Andreas,

Sorry I can't share the new TRM here.
The new version of TRM will be release by the TRM team on ti.com.

Regards,
Rishabh

0 Andreas Vogt57 over 6 years ago in reply to Rishabh Garg

Intellectual 730 points

Hi Rishabh,

ok thanks. Do you know a release date?

My company has a NDA with TI. Can this change your decision?

Regards,
Andreas

0 Rishabh Garg over 6 years ago in reply to Andreas Vogt57

TI__Guru 55685 points

Hi Andreas,

Do you have latest TDA3x TRM? Can you check the section 5.3.7 here:www.ti.com/.../spruie7c.pdf

Regards,
Rishabh

0 Mariya Petkova over 6 years ago in reply to Andreas Vogt57

TI__Expert 4885 points

Andreas Vogt57 , Rishabh Garg,

This section is planned to be added to the version B of the TRM, that is not officially released yet.

Andreas Vogt57 (5271409), you should wait for the official release of the TRM. The process of its release is started, it may takes a couple of weeks before it will be on ti.com and CDDS.

Regards,
Mariya

0 Rishabh Garg over 6 years ago in reply to Mariya Petkova

TI__Guru 55685 points

Hi Mariya,

Yes the official release for TDA2P is not available.
But the section Andreas is looking for is available in TDA3 TRM so that should be ok.

Regards,
Rishabh

0 Andreas Vogt57 over 6 years ago in reply to Rishabh Garg

Intellectual 730 points

Thanks

Regards,
Andreas

0 Rishabh Garg over 6 years ago in reply to Andreas Vogt57

TI__Guru 55685 points

Hi Andreas,

I am closing this thread as there are no further questions.

Regards,
Rishabh

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TDA2Px M4 IPU AMMU Questions