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CCS/TMS320C6678: DDR3 Initialization and address map

HaiShan Lin
Prodigy 100 points
Part Number: TMS320C6678

Tool/software: Code Composer Studio

Hi All,

I am learning DDR3 initialization using KeyStone Architecture DDR3 Memory Controller User Guide file.

I can't understand the description about  Address Mapping and SDRAM Configuration Register(SDCFG) in KeyStone Architecture DDR3 Memory Controller User Guide file.

If I want to used 8GB DDR3 and 2 chip select lines ,What should I set the SDCFG register? And what is the logical address(0x8000 0000~0xffff ffff) used for DCE0# or DCE1# ?

Hope for a table detailed described the logical address and physical address relations.

Thanks &Regards,

HaiShan

  • 0
    TI__Guru* 85960 points
    HaiShan, a lot of the SDCFG register configuration will depend on the memory you are using (row size, cas latency, etc). Please refer to the DDR datasheet for these values. Also, board simulations will determine parameters such as ODT and drive strength. The SDCFG is used by the controller to during initialization to program the MR registers in the DDR3.

    Regards,
    James
  • 0 in reply to JJD
    Prodigy 100 points

    Hi,

    Firstly,thanks for your reply.

    In fact,I truly want to know is how I can confirm the logical address located in which hardware.

    I know what the address means depend on the SDCFG and XMC registers configurations.

    Suposse the XMC register is set to default (map physical address 0x8 0000 0000~0x8 7fff ffff),and the SDCFG is set to 0x6306 2ABA(IBANK_POS = 0,IBANK = 8,EBANK =1,PAGESIZE = 2).

    Then, which logical address(0x8000 0000 ~0xffff ffff) is located at DDR connected with DEC#0 and which is with  DEC#1?

    I know it's shown on Table2-5 and  Table2-6 in SPRUGV8.pdf ,but I just can't clearly undestand the description.

    Could you please show me with the detailed address as an example?

    Thanks ,

    HaiShan

  • 0 in reply to HaiShan Lin
    TI__Guru* 85960 points
    HaiShan, the configuration in table 2-5 shows an example of interleaving 16 banks at one time. With PAGESIZE=2 and 3 bank bits, you have 13 address bits per page in each device. So I believe it should be this:

    0x8000 0000 - 0x0x8000 03FF Page 0, bank 0, device 0
    0x8000 0400 - 0x0x8000 07FF Page 0, bank 1, device 0
    0x8000 0800 - 0x0x8000 0BFF Page 0, bank 2, device 0
    0x8000 0C00 - 0x0x8000 0FFF Page 0, bank 3, device 0
    0x8000 1000 - 0x0x8000 03FF Page 0, bank 4, device 0
    0x8000 1400 - 0x0x8000 07FF Page 0, bank 5, device 0
    0x8000 1800 - 0x0x8000 0BFF Page 0, bank 6, device 0
    0x8000 1C00 - 0x0x8000 1FFF Page 0, bank 7, device 0
    0x8000 2000 - 0x0x8000 23FF Page 0, bank 0, device 1
    0x8000 2400 - 0x0x8000 27FF Page 0, bank 1, device 1
    0x8000 2800 - 0x0x8000 2BFF Page 0, bank 2, device 1
    0x8000 2C00 - 0x0x8000 2FFF Page 0, bank 3, device 1
    0x8000 3000 - 0x0x8000 33FF Page 0, bank 4, device 1
    0x8000 3400 - 0x0x8000 37FF Page 0, bank 5, device 1
    0x8000 3800 - 0x0x8000 3BFF Page 0, bank 6, device 1
    0x8000 3C00 - 0x0x8000 3FFF Page 0, bank 7, device 1

    0x8000 4000 - 0x0x8000 43FF Page 1, bank 0, device 0
    etc.

    The table tries to describe this by showing from left to right the components of the address from MSB->LSB

    Regards,
    James
  • 0 in reply to JJD
    Prodigy 100 points

    Hi James,

    Thanks a lot for your explanation. I see it completely now.

    Regards,

    HaiShan