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66AK2G12: checking the schematic

Naoki Kawada
Guru 19890 points
Part Number: 66AK2G12

Hi,

I`m now checking my customer`s schematic because of their 1st prototype using 66AK2G12. Now I have some questions:

1. My customer will not use USB1. In this case, can we leave all USB related pins (B20, A20, E20, A21, B21, D20) floating ?
2. My customer will not use PCIe. In this case, can we leave both PCIE_CLK_P and PCIE_CLK_N  floating ? It seems the datasheet does not mention so much. Now I`m wondering if these pin should be handled like other unused differential clocks. Please take a look at 5.9.3.2 Optional LVDS Clock Inputs Not Used in the data sheet and let me know your comments. In addition, how about PCIE_REFRES ? is it okay to leave it floating ?

Best Regards,
NK

  • 0
    Guru 19890 points
    An additional question.

    3. The datasheet says bulk bypass caps are required for DDR. Take a look at 7.1.2.8 Bulk Bypass Capacitors. If you see in the EVM schematic , which one is regarded as bulk caps to meet this spec ?

    Best Regards,
    NK
  • 0 in reply to Naoki Kawada
    Guru 19890 points
    Sorry, As for question 1 and 2, the following footnote in the datasheet would answersto my questions. Please let me know if i`m wrong.

    NOTE
    All other unused signal balls without Pad Configuration Register can be left unconnected.

    Ok, could you please let me know your comment especially for #3 ?

    Best Regards,
    NK
  • 0 in reply to Naoki Kawada
    TI__Guru**** 161600 points
    Hi Naoki,

    The schematic may differ from the Datasheet, because it was designed ahead with preliminary documentation. This is why we always recommend to refer to the datasheet in case of any differences between reference designs and datasheet.

    Best Regards,
    Yordan
  • 0 in reply to Yordan Kovachev
    Guru 19890 points
    Hi Yordan,

    I understand the differences could happen between evm schematic and datasheet. Let me clarify; as for #3, you meant the K2G12 evm did not have intentional bulk bypass caps implemented. Correct ?

    Best Regards,
    NK
  • 0 in reply to Naoki Kawada
    TI__Mastermind 42545 points
    Hi Naoki,
    1) I recommend that you include the resistor connected to D20 but the remaining pins may be left unconnected.
    2) Please include the connection to PCIE_REFRES. The PCIE_CLK_P/N should be terminated like other unused differential clocks.
    3) The EVM design does include 22uF capacitors on the VDD_DDR rail. These would be considered bulk capacitors. Ultimately the capacitors needed should be determined by PDN simulation of the customers PCB design.
    Regards, Bill
  • 0 in reply to Bill Taboada
    Guru 19890 points

    Hi Bill,

    Thank you for your support. Understood. If needed, please consider to update the datasheet for 1 and 2.

    Best Regards,
    NK