Synchronised system clock for Real Time Video Streaming...

Colin Reid

Hi,

In the VPIF user guide it states in section 2.13.2 that; "The BT.1120 mode also requires a 27MHz ssytem clock that is synchronised to the video input clock.". Figure 21 of this section shows an external PLL/Divider providing a 27MHz clock to the "Stream parser I/O" block, with the label m27_clk. How does this enter the DSP and is there a procedure to be followed in switching between the DEV_IMX clock and this synchronised clock?

Regards,

Colin

over 15 years ago

0 Paul.Yin over 15 years ago

TI__Genius 14405 points

Hi Colin,

I believe that block diagram is talking about syncing VPIF and TSIF. I believe m27_clk is basically TS_CLKIN of TSIF (sprueq2).

0 Colin Reid over 15 years ago in reply to Paul.Yin

Prodigy 70 points

Hi Paul,

Thanks for your reply. So for our application where we hope to received 1080p30 on the input VPIF, process this video, then output a new video stream on the VPIF output port in real time, there is no synchronisation constaint on the system clock of the DSP?

Regards,

Colin

0 Paul.Yin over 15 years ago in reply to Colin Reid

TI__Genius 14405 points

No, no constraint from the DSP.

regards,

Paul

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Synchronised system clock for Real Time Video Streaming...