The general sequence of TSIF

hello all:
  When I tested the TSIF0 interface as a receiver and which works in the  model of parallel and synchronous,I came cross the following problems:
1. Whether I only need  the following eleven pins or more?
    TS0_CLKIN(TSIF0 receive clock input)
    TS0_EN_WAITO(date enable)
    TS0_PSTIN(packet start)
    TSDIN0——TSDIN7(data)
2. The above pins,If there are no problems ,then I encounter another problem(the interrupt function tsif_isr can't be executed in the driver) when I use the

follwoing application to receive any Packets(Bypass model,only use write ring buffer 7),the following contents show the  general sequence of my application:

main()
{
    /* Open TSIF Control and Data Channels */
    tsif_rx_ctl_fd = open("/dev/hd_tsif0_rxcontrol", O_RDWR);
    tsif_rx_pid7_fd = open("/dev/hd_tsif0_rxfilter7", O_RDWR);

    rx_pid7_file_size =(rx_pid7_file_size / (192 * ONE_RING_SIZE)) * (192 * ONE_RING_SIZE);
    read_pid7_data_buf = (unsigned char *)malloc(rx_pid7_file_size);   
    ptr_pid7_save_buf = (int *)read_pid7_data_buf;
    rx_pid7_buf_size = mmap_len;
    rx_pid7_addr = mmap(NULL, rx_pid7_buf_size, PROT_READ | PROT_WRITE, MAP_SHARED,tsif_rx_pid7_fd, buffer.offset);

    rx_pid7_cfg.if_mode =TSIF_IF_PARALLEL_SYNC
    rx_pid7_cfg.filter_mode=TSIF_PID_FILTER_BYPASS,
    rx_pid7_cfg.stream_mode=TSIF_STREAM_NON_TS
    ret = ioctl(tsif_rx_ctl_fd, TSIF_SET_RX_CONFIG, &rx_pid7_cfg);

    /* Configure Ring Buffer for PID 7 */
    rx_pid7_ring_buf_cfg.pstart = rx_pid7_addr;
    rx_pid7_ring_buf_cfg.buf_size = RING_SIZE;
    ret =ioctl(tsif_rx_pid7_fd, TSIF_RX_RING_BUF_CONFIG,&rx_pid7_ring_buf_cfg);

    ret = ioctl(tsif_rx_ctl_fd, TSIF_BYPASS_ENABLE, 0);
   
    /* start rx */
    ret = ioctl(tsif_rx_ctl_fd, TSIF_START_RX, 0);

    pthread_create(&ptid7, NULL, receive_to_pid7, NULL);
-------------------------------------------
---------------------
}

void *receive_to_pid7(void *arg)
{
    int count, i;

    read_pid7_offset = 0;

    do {
        ret = ioctl(tsif_rx_pid7_fd, TSIF_WAIT_FOR_RX_COMPLETE, 0);
        if (ret != 0)
            printf
                ("TSIF_WAIT_FOR_RX_COMPLETE IOCTL for PID7 Failed\n");

        memcpy(read_pid7_data_buf + read_pid7_offset, rx_pid7_buf,
               ONE_RING_SIZE * 192);
        rx_pid7_buf += (ONE_RING_SIZE * 192);
        read_pid7_offset += (ONE_RING_SIZE * 192);

        if (rx_pid7_buf >= (char *)(rx_pid7_addr + mmap_len))
            rx_pid7_buf = (char *)rx_pid7_addr;
    } while (read_pid7_offset < rx_pid7_file_size);

    ------------
---------------------------------------------
}
When I send the Data from the MPEG2 TS Analyzer(designed by other engineers), and measure the siganl of the above eleven pins in the daughter card expander

(DC_P2),I can detection the signals with ondoscope. But when call the function "ret = ioctl(tsif_rx_pid7_fd, TSIF_WAIT_FOR_RX_COMPLETE, 0)" in thread

receive_to_pid7,I can't get any data,this is beacuse the data should be return by the following process in the driver (Bypass model):
(1)The interrupt funciton "tsif_isr" in driver will call "complete(&tsif_dev->rx_complete[7])"  to send the complete signal if the interrupt comes.
(2)The task "wait_for_completion_interruptible(&tsif_dev->rx_complete[minor])" in the function "tsif_data_ioctl" will be executed.
(3)Return the data to application by the following:
    case TSIF_WAIT_FOR_RX_COMPLETE:{
            wait_for_completion_interruptible(&tsif_dev->rx_complete[minor]);
            return 0;
            break;
        }
 That shows the fact if the application can't get any data ,this is because tsif_isr can't be executed, and this may be because the SDRAM writing address on write ring buffer channel 7 has not reached subtracted pointer address configured by ARM via the write ring buffer channel 7 subtraction register (RING_BUF_WR_CH7_SUB),but why? may be the TSIFO has not receive any data from the beginning.
  Are there something wrong with my 11 pins or the MPEG2 TS Analyzer(but the TS Analyzer has been passed test on other platform(baser on FPGA))? And
how the the SDRAM writing address on write ring buffer channel 7 move automatic?(by the fact hardware signal?)
  Thanks in advance.